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common/sfc_efx/base: update EF100 registers definitions

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Pick up all changes and extra definitions.

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
This commit is contained in:
Andrew Rybchenko 2021-10-11 17:48:21 +03:00 committed by Ferruh Yigit
parent b25c65e5c8
commit c4f4a0e60d
2 changed files with 85 additions and 23 deletions
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106
drivers/common/sfc_efx/base/efx_regs_ef100.h
View File

@ -323,12 +323,6 @@ extern "C" {
/* ES_RHEAD_BASE_EVENT */
#define ESF_GZ_E_TYPE_LBN 60
#define ESF_GZ_E_TYPE_WIDTH 4
#define ESE_GZ_EF100_EV_DRIVER 5
#define ESE_GZ_EF100_EV_MCDI 4
#define ESE_GZ_EF100_EV_CONTROL 3
#define ESE_GZ_EF100_EV_TX_TIMESTAMP 2
#define ESE_GZ_EF100_EV_TX_COMPLETION 1
#define ESE_GZ_EF100_EV_RX_PKTS 0
#define ESF_GZ_EV_EVQ_PHASE_LBN 59
#define ESF_GZ_EV_EVQ_PHASE_WIDTH 1
#define ESE_GZ_RHEAD_BASE_EVENT_STRUCT_SIZE 64
@ -467,6 +461,23 @@ extern "C" {
#define ESE_GZ_XIL_CFGBAR_VSEC_STRUCT_SIZE 96
/* ES_addr_spc */
#define ESF_GZ_ADDR_SPC_FORMAT_1_FUNCTION_LBN 28
#define ESF_GZ_ADDR_SPC_FORMAT_1_FUNCTION_WIDTH 8
#define ESF_GZ_ADDR_SPC_FORMAT_2_FUNCTION_LBN 24
#define ESF_GZ_ADDR_SPC_FORMAT_2_FUNCTION_WIDTH 12
#define ESF_GZ_ADDR_SPC_FORMAT_1_PROFILE_ID_LBN 24
#define ESF_GZ_ADDR_SPC_FORMAT_1_PROFILE_ID_WIDTH 4
#define ESF_GZ_ADDR_SPC_PASID_LBN 2
#define ESF_GZ_ADDR_SPC_PASID_WIDTH 22
#define ESF_GZ_ADDR_SPC_FORMAT_LBN 0
#define ESF_GZ_ADDR_SPC_FORMAT_WIDTH 2
#define ESE_GZ_ADDR_SPC_FORMAT_1 3
#define ESF_GZ_ADDR_SPC_FORMAT_2_PROFILE_ID_IDX_LBN 0
#define ESF_GZ_ADDR_SPC_FORMAT_2_PROFILE_ID_IDX_WIDTH 2
#define ESE_GZ_ADDR_SPC_STRUCT_SIZE 36
/* ES_rh_egres_hclass */
#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_LBN 15
#define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_WIDTH 1
@ -560,14 +571,18 @@ extern "C" {
#define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_WIDTH 16
#define ESF_GZ_RX_PREFIX_CSUM_FRAME_LBN 144
#define ESF_GZ_RX_PREFIX_CSUM_FRAME_WIDTH 16
#define ESF_GZ_RX_PREFIX_INGRESS_VPORT_LBN 128
#define ESF_GZ_RX_PREFIX_INGRESS_VPORT_WIDTH 16
#define ESF_GZ_RX_PREFIX_INGRESS_MPORT_LBN 128
#define ESF_GZ_RX_PREFIX_INGRESS_MPORT_WIDTH 16
#define ESF_GZ_RX_PREFIX_USER_MARK_LBN 96
#define ESF_GZ_RX_PREFIX_USER_MARK_WIDTH 32
#define ESF_GZ_RX_PREFIX_RSS_HASH_LBN 64
#define ESF_GZ_RX_PREFIX_RSS_HASH_WIDTH 32
#define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 32
#define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 32
#define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 34
#define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 30
#define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_LBN 33
#define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_WIDTH 1
#define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_LBN 32
#define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_WIDTH 1
#define ESF_GZ_RX_PREFIX_CLASS_LBN 16
#define ESF_GZ_RX_PREFIX_CLASS_WIDTH 16
#define ESF_GZ_RX_PREFIX_USER_FLAG_LBN 15
@ -674,12 +689,12 @@ extern "C" {
#define ESF_GZ_M2M_TRANSLATE_ADDR_WIDTH 1
#define ESF_GZ_M2M_RSVD_LBN 120
#define ESF_GZ_M2M_RSVD_WIDTH 2
#define ESF_GZ_M2M_ADDR_SPC_LBN 108
#define ESF_GZ_M2M_ADDR_SPC_WIDTH 12
#define ESF_GZ_M2M_ADDR_SPC_PASID_LBN 86
#define ESF_GZ_M2M_ADDR_SPC_PASID_WIDTH 22
#define ESF_GZ_M2M_ADDR_SPC_MODE_LBN 84
#define ESF_GZ_M2M_ADDR_SPC_MODE_WIDTH 2
#define ESF_GZ_M2M_ADDR_SPC_ID_DW0_LBN 84
#define ESF_GZ_M2M_ADDR_SPC_ID_DW0_WIDTH 32
#define ESF_GZ_M2M_ADDR_SPC_ID_DW1_LBN 116
#define ESF_GZ_M2M_ADDR_SPC_ID_DW1_WIDTH 4
#define ESF_GZ_M2M_ADDR_SPC_ID_LBN 84
#define ESF_GZ_M2M_ADDR_SPC_ID_WIDTH 36
#define ESF_GZ_M2M_LEN_MINUS_1_LBN 64
#define ESF_GZ_M2M_LEN_MINUS_1_WIDTH 20
#define ESF_GZ_M2M_ADDR_DW0_LBN 0
@ -722,12 +737,12 @@ extern "C" {
#define ESF_GZ_TX_SEG_TRANSLATE_ADDR_WIDTH 1
#define ESF_GZ_TX_SEG_RSVD2_LBN 120
#define ESF_GZ_TX_SEG_RSVD2_WIDTH 2
#define ESF_GZ_TX_SEG_ADDR_SPC_LBN 108
#define ESF_GZ_TX_SEG_ADDR_SPC_WIDTH 12
#define ESF_GZ_TX_SEG_ADDR_SPC_PASID_LBN 86
#define ESF_GZ_TX_SEG_ADDR_SPC_PASID_WIDTH 22
#define ESF_GZ_TX_SEG_ADDR_SPC_MODE_LBN 84
#define ESF_GZ_TX_SEG_ADDR_SPC_MODE_WIDTH 2
#define ESF_GZ_TX_SEG_ADDR_SPC_ID_DW0_LBN 84
#define ESF_GZ_TX_SEG_ADDR_SPC_ID_DW0_WIDTH 32
#define ESF_GZ_TX_SEG_ADDR_SPC_ID_DW1_LBN 116
#define ESF_GZ_TX_SEG_ADDR_SPC_ID_DW1_WIDTH 4
#define ESF_GZ_TX_SEG_ADDR_SPC_ID_LBN 84
#define ESF_GZ_TX_SEG_ADDR_SPC_ID_WIDTH 36
#define ESF_GZ_TX_SEG_RSVD_LBN 80
#define ESF_GZ_TX_SEG_RSVD_WIDTH 4
#define ESF_GZ_TX_SEG_LEN_LBN 64
@ -824,6 +839,12 @@ extern "C" {
/* Enum D2VIO_MSG_OP */
#define ESE_GZ_QUE_JBDNE 3
#define ESE_GZ_QUE_EVICT 2
#define ESE_GZ_QUE_EMPTY 1
#define ESE_GZ_NOP 0
/* Enum DESIGN_PARAMS */
#define ESE_EF100_DP_GZ_RX_MAX_RUNT 17
#define ESE_EF100_DP_GZ_VI_STRIDES 16
@ -871,6 +892,19 @@ extern "C" {
#define ESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE 256
#define ESE_GZ_PCI_EXPRESS_XCAP_HDR_SIZE 4
/* Enum RH_DSC_TYPE */
#define ESE_GZ_TX_TOMB 0xF
#define ESE_GZ_TX_VIO 0xE
#define ESE_GZ_TX_TSO_OVRRD 0x8
#define ESE_GZ_TX_D2CMP 0x7
#define ESE_GZ_TX_DATA 0x6
#define ESE_GZ_TX_D2M 0x5
#define ESE_GZ_TX_M2M 0x4
#define ESE_GZ_TX_SEG 0x3
#define ESE_GZ_TX_TSO 0x2
#define ESE_GZ_TX_OVRRD 0x1
#define ESE_GZ_TX_SEND 0x0
/* Enum RH_HCLASS_L2_CLASS */
#define ESE_GZ_RH_HCLASS_L2_CLASS_E2_0123VLAN 1
#define ESE_GZ_RH_HCLASS_L2_CLASS_OTHER 0
@ -907,6 +941,25 @@ extern "C" {
#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_VXLAN 1
#define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NONE 0
/* Enum SF_CTL_EVENT_SUBTYPE */
#define ESE_GZ_EF100_CTL_EV_EVQ_TIMEOUT 0x3
#define ESE_GZ_EF100_CTL_EV_FLUSH 0x2
#define ESE_GZ_EF100_CTL_EV_TIME_SYNC 0x1
#define ESE_GZ_EF100_CTL_EV_UNSOL_OVERFLOW 0x0
/* Enum SF_EVENT_TYPE */
#define ESE_GZ_EF100_EV_DRIVER 0x5
#define ESE_GZ_EF100_EV_MCDI 0x4
#define ESE_GZ_EF100_EV_CONTROL 0x3
#define ESE_GZ_EF100_EV_TX_TIMESTAMP 0x2
#define ESE_GZ_EF100_EV_TX_COMPLETION 0x1
#define ESE_GZ_EF100_EV_RX_PKTS 0x0
/* Enum SF_EW_EVENT_TYPE */
#define ESE_GZ_EF100_EWEV_VIRTQ_DESC 0x2
#define ESE_GZ_EF100_EWEV_TXQ_DESC 0x1
#define ESE_GZ_EF100_EWEV_64BIT 0x0
/* Enum TX_DESC_CSO_PARTIAL_EN */
#define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP 2
#define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP 1
@ -922,6 +975,15 @@ extern "C" {
#define ESE_GZ_TX_DESC_IP4_ID_INC_MOD16 2
#define ESE_GZ_TX_DESC_IP4_ID_INC_MOD15 1
#define ESE_GZ_TX_DESC_IP4_ID_NO_OP 0
/* Enum VIRTIO_NET_HDR_F */
#define ESE_GZ_NEEDS_CSUM 0x1
/* Enum VIRTIO_NET_HDR_GSO */
#define ESE_GZ_TCPV6 0x4
#define ESE_GZ_UDP 0x3
#define ESE_GZ_TCPV4 0x1
#define ESE_GZ_NONE 0x0
/*************************************************************************
* NOTE: the comment line above marks the end of the autogenerated section
*/

2
drivers/common/sfc_efx/base/rhead_rx.c
View File

@ -37,7 +37,7 @@ static const efx_rx_prefix_layout_t rhead_default_rx_prefix_layout = {
RHEAD_RX_PREFIX_FIELD(PARTIAL_TSTAMP, B_FALSE),
RHEAD_RX_PREFIX_FIELD(RSS_HASH, B_FALSE),
RHEAD_RX_PREFIX_FIELD(USER_MARK, B_FALSE),
RHEAD_RX_PREFIX_FIELD(INGRESS_VPORT, B_FALSE),
RHEAD_RX_PREFIX_FIELD(INGRESS_MPORT, B_FALSE),
RHEAD_RX_PREFIX_FIELD(CSUM_FRAME, B_TRUE),
RHEAD_RX_PREFIX_FIELD(VLAN_STRIP_TCI, B_TRUE),