d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

net/bnxt: support NAT for dest IP and port combination

Browse Source 
* Added support for NAT action for destination IP and port
  combination for Thor devices.
* Consolidated the encapsulation and NAT entries for scaling flows
  with NAT actions.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
This commit is contained in:
Kishore Padmanabha 2021-11-02 17:52:32 -07:00 committed by Ajit Khaparde
parent 136d164684
commit c674c133f1
6 changed files with 423 additions and 294 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
doc/guides/rel_notes/release_21_11.rst
View File

@ -153,6 +153,7 @@ New Features
* Added flow offload support for Thor.
* Implement support for tunnel offload.
* Updated HWRM API to version 1.10.2.44
* Added NAT support for dest IP and port combination.
* **Updated Cisco enic driver.**

586
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Mon May 17 15:30:41 2021 */
/* date: Wed Aug 25 14:37:06 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_ACT_HID_04bc] = 30,
[BNXT_ULP_ACT_HID_00a9] = 31,
[BNXT_ULP_ACT_HID_020f] = 32,
[BNXT_ULP_ACT_HID_04a9] = 33,
[BNXT_ULP_ACT_HID_01fc] = 34,
[BNXT_ULP_ACT_HID_04be] = 35,
[BNXT_ULP_ACT_HID_00ab] = 36,
[BNXT_ULP_ACT_HID_0211] = 37,
[BNXT_ULP_ACT_HID_04ab] = 38,
[BNXT_ULP_ACT_HID_01fe] = 39,
[BNXT_ULP_ACT_HID_0667] = 40,
[BNXT_ULP_ACT_HID_0254] = 41,
[BNXT_ULP_ACT_HID_03ba] = 42,
[BNXT_ULP_ACT_HID_0654] = 43,
[BNXT_ULP_ACT_HID_03a7] = 44,
[BNXT_ULP_ACT_HID_0669] = 45,
[BNXT_ULP_ACT_HID_0256] = 46,
[BNXT_ULP_ACT_HID_03bc] = 47,
[BNXT_ULP_ACT_HID_0656] = 48,
[BNXT_ULP_ACT_HID_03a9] = 49,
[BNXT_ULP_ACT_HID_021b] = 50,
[BNXT_ULP_ACT_HID_021c] = 51,
[BNXT_ULP_ACT_HID_021e] = 52,
[BNXT_ULP_ACT_HID_063f] = 53,
[BNXT_ULP_ACT_HID_0510] = 54,
[BNXT_ULP_ACT_HID_03c6] = 55,
[BNXT_ULP_ACT_HID_0082] = 56,
[BNXT_ULP_ACT_HID_06bb] = 57,
[BNXT_ULP_ACT_HID_021d] = 58,
[BNXT_ULP_ACT_HID_0641] = 59,
[BNXT_ULP_ACT_HID_0512] = 60,
[BNXT_ULP_ACT_HID_03c8] = 61,
[BNXT_ULP_ACT_HID_0084] = 62,
[BNXT_ULP_ACT_HID_06bd] = 63,
[BNXT_ULP_ACT_HID_06d7] = 64,
[BNXT_ULP_ACT_HID_02c4] = 65,
[BNXT_ULP_ACT_HID_042a] = 66,
[BNXT_ULP_ACT_HID_06c4] = 67,
[BNXT_ULP_ACT_HID_0417] = 68,
[BNXT_ULP_ACT_HID_06d9] = 69,
[BNXT_ULP_ACT_HID_02c6] = 70,
[BNXT_ULP_ACT_HID_042c] = 71,
[BNXT_ULP_ACT_HID_06c6] = 72,
[BNXT_ULP_ACT_HID_0419] = 73,
[BNXT_ULP_ACT_HID_0119] = 74,
[BNXT_ULP_ACT_HID_046f] = 75,
[BNXT_ULP_ACT_HID_05d5] = 76,
[BNXT_ULP_ACT_HID_0106] = 77,
[BNXT_ULP_ACT_HID_05c2] = 78,
[BNXT_ULP_ACT_HID_011b] = 79,
[BNXT_ULP_ACT_HID_0471] = 80,
[BNXT_ULP_ACT_HID_05d7] = 81,
[BNXT_ULP_ACT_HID_0108] = 82,
[BNXT_ULP_ACT_HID_05c4] = 83,
[BNXT_ULP_ACT_HID_00a2] = 84,
[BNXT_ULP_ACT_HID_00a4] = 85
[BNXT_ULP_ACT_HID_0153] = 33,
[BNXT_ULP_ACT_HID_04a9] = 34,
[BNXT_ULP_ACT_HID_01fc] = 35,
[BNXT_ULP_ACT_HID_04be] = 36,
[BNXT_ULP_ACT_HID_00ab] = 37,
[BNXT_ULP_ACT_HID_0211] = 38,
[BNXT_ULP_ACT_HID_0155] = 39,
[BNXT_ULP_ACT_HID_04ab] = 40,
[BNXT_ULP_ACT_HID_01fe] = 41,
[BNXT_ULP_ACT_HID_0667] = 42,
[BNXT_ULP_ACT_HID_0254] = 43,
[BNXT_ULP_ACT_HID_03ba] = 44,
[BNXT_ULP_ACT_HID_02fe] = 45,
[BNXT_ULP_ACT_HID_0654] = 46,
[BNXT_ULP_ACT_HID_03a7] = 47,
[BNXT_ULP_ACT_HID_0669] = 48,
[BNXT_ULP_ACT_HID_0256] = 49,
[BNXT_ULP_ACT_HID_03bc] = 50,
[BNXT_ULP_ACT_HID_0300] = 51,
[BNXT_ULP_ACT_HID_0656] = 52,
[BNXT_ULP_ACT_HID_03a9] = 53,
[BNXT_ULP_ACT_HID_021b] = 54,
[BNXT_ULP_ACT_HID_021c] = 55,
[BNXT_ULP_ACT_HID_021e] = 56,
[BNXT_ULP_ACT_HID_063f] = 57,
[BNXT_ULP_ACT_HID_0510] = 58,
[BNXT_ULP_ACT_HID_03c6] = 59,
[BNXT_ULP_ACT_HID_0082] = 60,
[BNXT_ULP_ACT_HID_06bb] = 61,
[BNXT_ULP_ACT_HID_021d] = 62,
[BNXT_ULP_ACT_HID_0641] = 63,
[BNXT_ULP_ACT_HID_0512] = 64,
[BNXT_ULP_ACT_HID_03c8] = 65,
[BNXT_ULP_ACT_HID_0084] = 66,
[BNXT_ULP_ACT_HID_06bd] = 67,
[BNXT_ULP_ACT_HID_06d7] = 68,
[BNXT_ULP_ACT_HID_02c4] = 69,
[BNXT_ULP_ACT_HID_042a] = 70,
[BNXT_ULP_ACT_HID_036e] = 71,
[BNXT_ULP_ACT_HID_06c4] = 72,
[BNXT_ULP_ACT_HID_0417] = 73,
[BNXT_ULP_ACT_HID_06d9] = 74,
[BNXT_ULP_ACT_HID_02c6] = 75,
[BNXT_ULP_ACT_HID_042c] = 76,
[BNXT_ULP_ACT_HID_0370] = 77,
[BNXT_ULP_ACT_HID_06c6] = 78,
[BNXT_ULP_ACT_HID_0419] = 79,
[BNXT_ULP_ACT_HID_0119] = 80,
[BNXT_ULP_ACT_HID_046f] = 81,
[BNXT_ULP_ACT_HID_05d5] = 82,
[BNXT_ULP_ACT_HID_0519] = 83,
[BNXT_ULP_ACT_HID_0106] = 84,
[BNXT_ULP_ACT_HID_05c2] = 85,
[BNXT_ULP_ACT_HID_011b] = 86,
[BNXT_ULP_ACT_HID_0471] = 87,
[BNXT_ULP_ACT_HID_05d7] = 88,
[BNXT_ULP_ACT_HID_051b] = 89,
[BNXT_ULP_ACT_HID_0108] = 90,
[BNXT_ULP_ACT_HID_05c4] = 91,
[BNXT_ULP_ACT_HID_00a2] = 92,
[BNXT_ULP_ACT_HID_00a4] = 93
};
/* Array for the act matcher list */
@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 3
},
[33] = {
.act_hid = BNXT_ULP_ACT_HID_04a9,
.act_hid = BNXT_ULP_ACT_HID_0153,
.act_pattern_id = 3,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[34] = {
.act_hid = BNXT_ULP_ACT_HID_01fc,
.act_hid = BNXT_ULP_ACT_HID_04a9,
.act_pattern_id = 4,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
@ -452,108 +458,142 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 3
},
[35] = {
.act_hid = BNXT_ULP_ACT_HID_04be,
.act_hid = BNXT_ULP_ACT_HID_01fc,
.act_pattern_id = 5,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[36] = {
.act_hid = BNXT_ULP_ACT_HID_00ab,
.act_hid = BNXT_ULP_ACT_HID_04be,
.act_pattern_id = 6,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[37] = {
.act_hid = BNXT_ULP_ACT_HID_0211,
.act_hid = BNXT_ULP_ACT_HID_00ab,
.act_pattern_id = 7,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[38] = {
.act_hid = BNXT_ULP_ACT_HID_04ab,
.act_hid = BNXT_ULP_ACT_HID_0211,
.act_pattern_id = 8,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[39] = {
.act_hid = BNXT_ULP_ACT_HID_01fe,
.act_hid = BNXT_ULP_ACT_HID_0155,
.act_pattern_id = 9,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[40] = {
.act_hid = BNXT_ULP_ACT_HID_0667,
.act_hid = BNXT_ULP_ACT_HID_04ab,
.act_pattern_id = 10,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[41] = {
.act_hid = BNXT_ULP_ACT_HID_0254,
.act_hid = BNXT_ULP_ACT_HID_01fe,
.act_pattern_id = 11,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[42] = {
.act_hid = BNXT_ULP_ACT_HID_03ba,
.act_hid = BNXT_ULP_ACT_HID_0667,
.act_pattern_id = 12,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[43] = {
.act_hid = BNXT_ULP_ACT_HID_0654,
.act_hid = BNXT_ULP_ACT_HID_0254,
.act_pattern_id = 13,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[44] = {
.act_hid = BNXT_ULP_ACT_HID_03a7,
.act_hid = BNXT_ULP_ACT_HID_03ba,
.act_pattern_id = 14,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[45] = {
.act_hid = BNXT_ULP_ACT_HID_02fe,
.act_pattern_id = 15,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[46] = {
.act_hid = BNXT_ULP_ACT_HID_0654,
.act_pattern_id = 16,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[47] = {
.act_hid = BNXT_ULP_ACT_HID_03a7,
.act_pattern_id = 17,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
@ -563,68 +603,80 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[45] = {
.act_hid = BNXT_ULP_ACT_HID_0669,
.act_pattern_id = 15,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[46] = {
.act_hid = BNXT_ULP_ACT_HID_0256,
.act_pattern_id = 16,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[47] = {
.act_hid = BNXT_ULP_ACT_HID_03bc,
.act_pattern_id = 17,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[48] = {
.act_hid = BNXT_ULP_ACT_HID_0656,
.act_hid = BNXT_ULP_ACT_HID_0669,
.act_pattern_id = 18,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[49] = {
.act_hid = BNXT_ULP_ACT_HID_03a9,
.act_hid = BNXT_ULP_ACT_HID_0256,
.act_pattern_id = 19,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[50] = {
.act_hid = BNXT_ULP_ACT_HID_03bc,
.act_pattern_id = 20,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[51] = {
.act_hid = BNXT_ULP_ACT_HID_0300,
.act_pattern_id = 21,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[52] = {
.act_hid = BNXT_ULP_ACT_HID_0656,
.act_pattern_id = 22,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[50] = {
[53] = {
.act_hid = BNXT_ULP_ACT_HID_03a9,
.act_pattern_id = 23,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[54] = {
.act_hid = BNXT_ULP_ACT_HID_021b,
.act_pattern_id = 0,
.app_sig = 0,
@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[51] = {
[55] = {
.act_hid = BNXT_ULP_ACT_HID_021c,
.act_pattern_id = 1,
.app_sig = 0,
@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[52] = {
[56] = {
.act_hid = BNXT_ULP_ACT_HID_021e,
.act_pattern_id = 2,
.app_sig = 0,
@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[53] = {
[57] = {
.act_hid = BNXT_ULP_ACT_HID_063f,
.act_pattern_id = 3,
.app_sig = 0,
@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[54] = {
[58] = {
.act_hid = BNXT_ULP_ACT_HID_0510,
.act_pattern_id = 4,
.app_sig = 0,
@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[55] = {
[59] = {
.act_hid = BNXT_ULP_ACT_HID_03c6,
.act_pattern_id = 5,
.app_sig = 0,
@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[56] = {
[60] = {
.act_hid = BNXT_ULP_ACT_HID_0082,
.act_pattern_id = 6,
.app_sig = 0,
@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[57] = {
[61] = {
.act_hid = BNXT_ULP_ACT_HID_06bb,
.act_pattern_id = 7,
.app_sig = 0,
@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[58] = {
[62] = {
.act_hid = BNXT_ULP_ACT_HID_021d,
.act_pattern_id = 8,
.app_sig = 0,
@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[59] = {
[63] = {
.act_hid = BNXT_ULP_ACT_HID_0641,
.act_pattern_id = 9,
.app_sig = 0,
@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[60] = {
[64] = {
.act_hid = BNXT_ULP_ACT_HID_0512,
.act_pattern_id = 10,
.app_sig = 0,
@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[61] = {
[65] = {
.act_hid = BNXT_ULP_ACT_HID_03c8,
.act_pattern_id = 11,
.app_sig = 0,
@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[62] = {
[66] = {
.act_hid = BNXT_ULP_ACT_HID_0084,
.act_pattern_id = 12,
.app_sig = 0,
@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[63] = {
[67] = {
.act_hid = BNXT_ULP_ACT_HID_06bd,
.act_pattern_id = 13,
.app_sig = 0,
@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
[64] = {
[68] = {
.act_hid = BNXT_ULP_ACT_HID_06d7,
.act_pattern_id = 0,
.app_sig = 0,
@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[65] = {
[69] = {
.act_hid = BNXT_ULP_ACT_HID_02c4,
.act_pattern_id = 1,
.app_sig = 0,
@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[66] = {
[70] = {
.act_hid = BNXT_ULP_ACT_HID_042a,
.act_pattern_id = 2,
.app_sig = 0,
@ -799,66 +851,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[67] = {
.act_hid = BNXT_ULP_ACT_HID_06c4,
[71] = {
.act_hid = BNXT_ULP_ACT_HID_036e,
.act_pattern_id = 3,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[68] = {
.act_hid = BNXT_ULP_ACT_HID_0417,
.act_pattern_id = 4,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[69] = {
.act_hid = BNXT_ULP_ACT_HID_06d9,
.act_pattern_id = 5,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[70] = {
.act_hid = BNXT_ULP_ACT_HID_02c6,
.act_pattern_id = 6,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[71] = {
.act_hid = BNXT_ULP_ACT_HID_042c,
.act_pattern_id = 7,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[72] = {
.act_hid = BNXT_ULP_ACT_HID_06c6,
.act_pattern_id = 8,
.act_hid = BNXT_ULP_ACT_HID_06c4,
.act_pattern_id = 4,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
@ -866,11 +873,10 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 5
},
[73] = {
.act_hid = BNXT_ULP_ACT_HID_0419,
.act_pattern_id = 9,
.act_hid = BNXT_ULP_ACT_HID_0417,
.act_pattern_id = 5,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
@ -879,55 +885,53 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 5
},
[74] = {
.act_hid = BNXT_ULP_ACT_HID_0119,
.act_pattern_id = 10,
.act_hid = BNXT_ULP_ACT_HID_06d9,
.act_pattern_id = 6,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[75] = {
.act_hid = BNXT_ULP_ACT_HID_046f,
.act_pattern_id = 11,
.act_hid = BNXT_ULP_ACT_HID_02c6,
.act_pattern_id = 7,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[76] = {
.act_hid = BNXT_ULP_ACT_HID_05d5,
.act_pattern_id = 12,
.act_hid = BNXT_ULP_ACT_HID_042c,
.act_pattern_id = 8,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[77] = {
.act_hid = BNXT_ULP_ACT_HID_0106,
.act_pattern_id = 13,
.act_hid = BNXT_ULP_ACT_HID_0370,
.act_pattern_id = 9,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[78] = {
.act_hid = BNXT_ULP_ACT_HID_05c2,
.act_pattern_id = 14,
.act_hid = BNXT_ULP_ACT_HID_06c6,
.act_pattern_id = 10,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
@ -935,67 +939,159 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 5
},
[79] = {
.act_hid = BNXT_ULP_ACT_HID_011b,
.act_pattern_id = 15,
.act_hid = BNXT_ULP_ACT_HID_0419,
.act_pattern_id = 11,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[80] = {
.act_hid = BNXT_ULP_ACT_HID_0471,
.act_pattern_id = 16,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[81] = {
.act_hid = BNXT_ULP_ACT_HID_05d7,
.act_pattern_id = 17,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[82] = {
.act_hid = BNXT_ULP_ACT_HID_0108,
.act_pattern_id = 18,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[80] = {
.act_hid = BNXT_ULP_ACT_HID_0119,
.act_pattern_id = 12,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[81] = {
.act_hid = BNXT_ULP_ACT_HID_046f,
.act_pattern_id = 13,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[82] = {
.act_hid = BNXT_ULP_ACT_HID_05d5,
.act_pattern_id = 14,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[83] = {
.act_hid = BNXT_ULP_ACT_HID_05c4,
.act_hid = BNXT_ULP_ACT_HID_0519,
.act_pattern_id = 15,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[84] = {
.act_hid = BNXT_ULP_ACT_HID_0106,
.act_pattern_id = 16,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[85] = {
.act_hid = BNXT_ULP_ACT_HID_05c2,
.act_pattern_id = 17,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[86] = {
.act_hid = BNXT_ULP_ACT_HID_011b,
.act_pattern_id = 18,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[87] = {
.act_hid = BNXT_ULP_ACT_HID_0471,
.act_pattern_id = 19,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[88] = {
.act_hid = BNXT_ULP_ACT_HID_05d7,
.act_pattern_id = 20,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[89] = {
.act_hid = BNXT_ULP_ACT_HID_051b,
.act_pattern_id = 21,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[90] = {
.act_hid = BNXT_ULP_ACT_HID_0108,
.act_pattern_id = 22,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[84] = {
[91] = {
.act_hid = BNXT_ULP_ACT_HID_05c4,
.act_pattern_id = 23,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
[92] = {
.act_hid = BNXT_ULP_ACT_HID_00a2,
.act_pattern_id = 0,
.app_sig = 0,
@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
[85] = {
[93] = {
.act_hid = BNXT_ULP_ACT_HID_00a4,
.act_pattern_id = 1,
.app_sig = 0,

18
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Fri Aug 20 17:59:14 2021 */
/* date: Thu Aug 26 17:43:36 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@ -20,7 +20,7 @@
#define BNXT_ULP_CLASS_HID_SHFTL 28
#define BNXT_ULP_CLASS_HID_MASK 65535
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
#define BNXT_ULP_ACT_HID_HIGH_PRIME 3793
#define BNXT_ULP_ACT_HID_SHFTR 27
@ -29,7 +29,7 @@
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278
#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277
#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
@ -50,11 +50,11 @@
#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
#define ULP_THOR_ACT_TBL_LIST_SIZE 36
#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16
@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid {
BNXT_ULP_ACT_HID_04bc = 0x04bc,
BNXT_ULP_ACT_HID_00a9 = 0x00a9,
BNXT_ULP_ACT_HID_020f = 0x020f,
BNXT_ULP_ACT_HID_0153 = 0x0153,
BNXT_ULP_ACT_HID_04a9 = 0x04a9,
BNXT_ULP_ACT_HID_01fc = 0x01fc,
BNXT_ULP_ACT_HID_04be = 0x04be,
BNXT_ULP_ACT_HID_00ab = 0x00ab,
BNXT_ULP_ACT_HID_0211 = 0x0211,
BNXT_ULP_ACT_HID_0155 = 0x0155,
BNXT_ULP_ACT_HID_04ab = 0x04ab,
BNXT_ULP_ACT_HID_01fe = 0x01fe,
BNXT_ULP_ACT_HID_0667 = 0x0667,
BNXT_ULP_ACT_HID_0254 = 0x0254,
BNXT_ULP_ACT_HID_03ba = 0x03ba,
BNXT_ULP_ACT_HID_02fe = 0x02fe,
BNXT_ULP_ACT_HID_0654 = 0x0654,
BNXT_ULP_ACT_HID_03a7 = 0x03a7,
BNXT_ULP_ACT_HID_0669 = 0x0669,
BNXT_ULP_ACT_HID_0256 = 0x0256,
BNXT_ULP_ACT_HID_03bc = 0x03bc,
BNXT_ULP_ACT_HID_0300 = 0x0300,
BNXT_ULP_ACT_HID_0656 = 0x0656,
BNXT_ULP_ACT_HID_03a9 = 0x03a9,
BNXT_ULP_ACT_HID_021b = 0x021b,
@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid {
BNXT_ULP_ACT_HID_06d7 = 0x06d7,
BNXT_ULP_ACT_HID_02c4 = 0x02c4,
BNXT_ULP_ACT_HID_042a = 0x042a,
BNXT_ULP_ACT_HID_036e = 0x036e,
BNXT_ULP_ACT_HID_06c4 = 0x06c4,
BNXT_ULP_ACT_HID_0417 = 0x0417,
BNXT_ULP_ACT_HID_06d9 = 0x06d9,
BNXT_ULP_ACT_HID_02c6 = 0x02c6,
BNXT_ULP_ACT_HID_042c = 0x042c,
BNXT_ULP_ACT_HID_0370 = 0x0370,
BNXT_ULP_ACT_HID_06c6 = 0x06c6,
BNXT_ULP_ACT_HID_0419 = 0x0419,
BNXT_ULP_ACT_HID_0119 = 0x0119,
BNXT_ULP_ACT_HID_046f = 0x046f,
BNXT_ULP_ACT_HID_05d5 = 0x05d5,
BNXT_ULP_ACT_HID_0519 = 0x0519,
BNXT_ULP_ACT_HID_0106 = 0x0106,
BNXT_ULP_ACT_HID_05c2 = 0x05c2,
BNXT_ULP_ACT_HID_011b = 0x011b,
BNXT_ULP_ACT_HID_0471 = 0x0471,
BNXT_ULP_ACT_HID_05d7 = 0x05d7,
BNXT_ULP_ACT_HID_051b = 0x051b,
BNXT_ULP_ACT_HID_0108 = 0x0108,
BNXT_ULP_ACT_HID_05c4 = 0x05c4,
BNXT_ULP_ACT_HID_00a2 = 0x00a2,

14
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Tue Aug 17 12:16:42 2021 */
/* date: Thu Aug 26 17:43:36 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.count = 64
.count = 2048
},
{
.app_id = 0,
@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.count = 64
.count = 2048
},
{
.app_id = 0,
@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
.count = 32
},
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 272

2
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Fri Aug 20 18:05:25 2021 */
/* date: Wed Aug 25 16:41:37 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"

96
drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Tue Jun 1 16:05:30 2021 */
/* date: Wed Aug 25 14:37:06 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@ -35,7 +35,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
/* act_tid: 3, ingress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 6,
.num_tbls = 7,
.start_tbl_idx = 12,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@ -46,30 +46,30 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 5,
.start_tbl_idx = 18,
.start_tbl_idx = 19,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 20,
.cond_start_idx = 21,
.cond_nums = 0 }
},
/* act_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 6,
.start_tbl_idx = 23,
.num_tbls = 7,
.start_tbl_idx = 24,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 28,
.cond_start_idx = 29,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 6,
.start_tbl_idx = 29,
.start_tbl_idx = 31,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 33,
.cond_start_idx = 35,
.cond_nums = 0 }
}
};
@ -322,6 +322,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.result_bit_size = 34,
.result_num_fields = 2
},
{ /* act_tid: 3, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1023,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 15,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@ -332,7 +343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 15,
.cond_start_idx = 16,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@ -351,7 +362,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 16,
.cond_start_idx = 17,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
@ -370,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 17,
.cond_start_idx = 18,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
@ -389,7 +400,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 18,
.cond_start_idx = 19,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@ -410,7 +421,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 18,
.cond_start_idx = 19,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@ -429,7 +440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 19,
.cond_start_idx = 20,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@ -449,7 +460,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 20,
.cond_start_idx = 21,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@ -468,7 +479,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 21,
.cond_start_idx = 22,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
@ -489,7 +500,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 23,
.cond_start_idx = 24,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@ -508,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 24,
.cond_start_idx = 25,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@ -528,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 26,
.cond_start_idx = 27,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@ -538,6 +549,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.result_num_fields = 26,
.encap_num_fields = 11
},
{ /* act_tid: 5, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1023,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 29,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@ -548,7 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 28,
.cond_start_idx = 30,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@ -567,7 +589,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 29,
.cond_start_idx = 31,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
@ -586,7 +608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 30,
.cond_start_idx = 32,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
@ -605,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 31,
.cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@ -626,7 +648,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 31,
.cond_start_idx = 33,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@ -645,7 +667,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 32,
.cond_start_idx = 34,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@ -665,7 +687,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 33,
.cond_start_idx = 35,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@ -684,7 +706,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 34,
.cond_start_idx = 36,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
@ -705,7 +727,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 35,
.cond_start_idx = 37,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
@ -726,7 +748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 36,
.cond_start_idx = 38,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
@ -747,7 +769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 37,
.cond_start_idx = 39,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@ -766,7 +788,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 38,
.cond_start_idx = 40,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@ -844,6 +866,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
/* cond_execute: act_tid: 3, control.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
/* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
@ -900,6 +927,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
},
/* cond_execute: act_tid: 5, control.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
/* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,