net/thunderx/base: add hardware API
add nicvf hardware specific APIs for initialization and configuration. Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Signed-off-by: Maciej Czekaj <maciej.czekaj@caviumnetworks.com> Signed-off-by: Kamil Rytarowski <kamil.rytarowski@caviumnetworks.com> Signed-off-by: Zyta Szpak <zyta.szpak@semihalf.com> Signed-off-by: Slawomir Rosek <slawomir.rosek@semihalf.com> Signed-off-by: Radoslaw Biernacki <rad@semihalf.com>
This commit is contained in:
Jerin Jacob
Bruce Richardson
parent
966e225c23
commit
c747e72b7d
731
drivers/net/thunderx/base/nicvf_hw.c
Normal file
731
drivers/net/thunderx/base/nicvf_hw.c
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@ -0,0 +1,731 @@
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/*
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* BSD LICENSE
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*
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* Copyright (C) Cavium networks Ltd. 2016.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Cavium networks nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <unistd.h>
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#include <math.h>
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#include <errno.h>
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "nicvf_plat.h"
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struct nicvf_reg_info {
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uint32_t offset;
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const char *name;
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};
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#define NICVF_REG_POLL_ITER_NR (10)
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#define NICVF_REG_POLL_DELAY_US (2000)
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#define NICVF_REG_INFO(reg) {reg, #reg}
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static const struct nicvf_reg_info nicvf_reg_tbl[] = {
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NICVF_REG_INFO(NIC_VF_CFG),
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NICVF_REG_INFO(NIC_VF_PF_MAILBOX_0_1),
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NICVF_REG_INFO(NIC_VF_INT),
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NICVF_REG_INFO(NIC_VF_INT_W1S),
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NICVF_REG_INFO(NIC_VF_ENA_W1C),
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NICVF_REG_INFO(NIC_VF_ENA_W1S),
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NICVF_REG_INFO(NIC_VNIC_RSS_CFG),
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NICVF_REG_INFO(NIC_VNIC_RQ_GEN_CFG),
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};
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static const struct nicvf_reg_info nicvf_multi_reg_tbl[] = {
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{NIC_VNIC_RSS_KEY_0_4 + 0, "NIC_VNIC_RSS_KEY_0"},
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{NIC_VNIC_RSS_KEY_0_4 + 8, "NIC_VNIC_RSS_KEY_1"},
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{NIC_VNIC_RSS_KEY_0_4 + 16, "NIC_VNIC_RSS_KEY_2"},
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{NIC_VNIC_RSS_KEY_0_4 + 24, "NIC_VNIC_RSS_KEY_3"},
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{NIC_VNIC_RSS_KEY_0_4 + 32, "NIC_VNIC_RSS_KEY_4"},
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{NIC_VNIC_TX_STAT_0_4 + 0, "NIC_VNIC_STAT_TX_OCTS"},
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{NIC_VNIC_TX_STAT_0_4 + 8, "NIC_VNIC_STAT_TX_UCAST"},
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{NIC_VNIC_TX_STAT_0_4 + 16, "NIC_VNIC_STAT_TX_BCAST"},
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{NIC_VNIC_TX_STAT_0_4 + 24, "NIC_VNIC_STAT_TX_MCAST"},
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{NIC_VNIC_TX_STAT_0_4 + 32, "NIC_VNIC_STAT_TX_DROP"},
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{NIC_VNIC_RX_STAT_0_13 + 0, "NIC_VNIC_STAT_RX_OCTS"},
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{NIC_VNIC_RX_STAT_0_13 + 8, "NIC_VNIC_STAT_RX_UCAST"},
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{NIC_VNIC_RX_STAT_0_13 + 16, "NIC_VNIC_STAT_RX_BCAST"},
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{NIC_VNIC_RX_STAT_0_13 + 24, "NIC_VNIC_STAT_RX_MCAST"},
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{NIC_VNIC_RX_STAT_0_13 + 32, "NIC_VNIC_STAT_RX_RED"},
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{NIC_VNIC_RX_STAT_0_13 + 40, "NIC_VNIC_STAT_RX_RED_OCTS"},
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{NIC_VNIC_RX_STAT_0_13 + 48, "NIC_VNIC_STAT_RX_ORUN"},
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{NIC_VNIC_RX_STAT_0_13 + 56, "NIC_VNIC_STAT_RX_ORUN_OCTS"},
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{NIC_VNIC_RX_STAT_0_13 + 64, "NIC_VNIC_STAT_RX_FCS"},
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{NIC_VNIC_RX_STAT_0_13 + 72, "NIC_VNIC_STAT_RX_L2ERR"},
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{NIC_VNIC_RX_STAT_0_13 + 80, "NIC_VNIC_STAT_RX_DRP_BCAST"},
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{NIC_VNIC_RX_STAT_0_13 + 88, "NIC_VNIC_STAT_RX_DRP_MCAST"},
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{NIC_VNIC_RX_STAT_0_13 + 96, "NIC_VNIC_STAT_RX_DRP_L3BCAST"},
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{NIC_VNIC_RX_STAT_0_13 + 104, "NIC_VNIC_STAT_RX_DRP_L3MCAST"},
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};
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static const struct nicvf_reg_info nicvf_qset_cq_reg_tbl[] = {
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_CFG),
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_CFG2),
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_THRESH),
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_BASE),
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_HEAD),
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_TAIL),
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_DOOR),
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_STATUS),
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_STATUS2),
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NICVF_REG_INFO(NIC_QSET_CQ_0_7_DEBUG),
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};
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static const struct nicvf_reg_info nicvf_qset_rq_reg_tbl[] = {
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NICVF_REG_INFO(NIC_QSET_RQ_0_7_CFG),
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NICVF_REG_INFO(NIC_QSET_RQ_0_7_STATUS0),
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NICVF_REG_INFO(NIC_QSET_RQ_0_7_STATUS1),
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};
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static const struct nicvf_reg_info nicvf_qset_sq_reg_tbl[] = {
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_CFG),
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_THRESH),
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_BASE),
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_HEAD),
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_TAIL),
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_DOOR),
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_STATUS),
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_DEBUG),
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_STATUS0),
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NICVF_REG_INFO(NIC_QSET_SQ_0_7_STATUS1),
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};
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static const struct nicvf_reg_info nicvf_qset_rbdr_reg_tbl[] = {
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NICVF_REG_INFO(NIC_QSET_RBDR_0_1_CFG),
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NICVF_REG_INFO(NIC_QSET_RBDR_0_1_THRESH),
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NICVF_REG_INFO(NIC_QSET_RBDR_0_1_BASE),
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NICVF_REG_INFO(NIC_QSET_RBDR_0_1_HEAD),
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NICVF_REG_INFO(NIC_QSET_RBDR_0_1_TAIL),
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NICVF_REG_INFO(NIC_QSET_RBDR_0_1_DOOR),
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NICVF_REG_INFO(NIC_QSET_RBDR_0_1_STATUS0),
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NICVF_REG_INFO(NIC_QSET_RBDR_0_1_STATUS1),
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NICVF_REG_INFO(NIC_QSET_RBDR_0_1_PRFCH_STATUS),
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};
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int
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nicvf_base_init(struct nicvf *nic)
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{
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nic->hwcap = 0;
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if (nic->subsystem_device_id == 0)
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return NICVF_ERR_BASE_INIT;
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if (nicvf_hw_version(nic) == NICVF_PASS2)
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nic->hwcap |= NICVF_CAP_TUNNEL_PARSING;
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return NICVF_OK;
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}
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/* dump on stdout if data is NULL */
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int
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nicvf_reg_dump(struct nicvf *nic, uint64_t *data)
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{
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uint32_t i, q;
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bool dump_stdout;
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dump_stdout = data ? 0 : 1;
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for (i = 0; i < NICVF_ARRAY_SIZE(nicvf_reg_tbl); i++)
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if (dump_stdout)
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nicvf_log("%24s = 0x%" PRIx64 "\n",
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nicvf_reg_tbl[i].name,
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nicvf_reg_read(nic, nicvf_reg_tbl[i].offset));
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else
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*data++ = nicvf_reg_read(nic, nicvf_reg_tbl[i].offset);
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for (i = 0; i < NICVF_ARRAY_SIZE(nicvf_multi_reg_tbl); i++)
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if (dump_stdout)
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nicvf_log("%24s = 0x%" PRIx64 "\n",
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nicvf_multi_reg_tbl[i].name,
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nicvf_reg_read(nic,
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nicvf_multi_reg_tbl[i].offset));
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else
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*data++ = nicvf_reg_read(nic,
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nicvf_multi_reg_tbl[i].offset);
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for (q = 0; q < MAX_CMP_QUEUES_PER_QS; q++)
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for (i = 0; i < NICVF_ARRAY_SIZE(nicvf_qset_cq_reg_tbl); i++)
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if (dump_stdout)
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nicvf_log("%30s(%d) = 0x%" PRIx64 "\n",
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nicvf_qset_cq_reg_tbl[i].name, q,
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nicvf_queue_reg_read(nic,
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nicvf_qset_cq_reg_tbl[i].offset, q));
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else
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*data++ = nicvf_queue_reg_read(nic,
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nicvf_qset_cq_reg_tbl[i].offset, q);
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for (q = 0; q < MAX_RCV_QUEUES_PER_QS; q++)
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for (i = 0; i < NICVF_ARRAY_SIZE(nicvf_qset_rq_reg_tbl); i++)
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if (dump_stdout)
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nicvf_log("%30s(%d) = 0x%" PRIx64 "\n",
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nicvf_qset_rq_reg_tbl[i].name, q,
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nicvf_queue_reg_read(nic,
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nicvf_qset_rq_reg_tbl[i].offset, q));
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else
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*data++ = nicvf_queue_reg_read(nic,
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nicvf_qset_rq_reg_tbl[i].offset, q);
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for (q = 0; q < MAX_SND_QUEUES_PER_QS; q++)
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for (i = 0; i < NICVF_ARRAY_SIZE(nicvf_qset_sq_reg_tbl); i++)
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if (dump_stdout)
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nicvf_log("%30s(%d) = 0x%" PRIx64 "\n",
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nicvf_qset_sq_reg_tbl[i].name, q,
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nicvf_queue_reg_read(nic,
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nicvf_qset_sq_reg_tbl[i].offset, q));
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else
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*data++ = nicvf_queue_reg_read(nic,
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nicvf_qset_sq_reg_tbl[i].offset, q);
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for (q = 0; q < MAX_RCV_BUF_DESC_RINGS_PER_QS; q++)
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for (i = 0; i < NICVF_ARRAY_SIZE(nicvf_qset_rbdr_reg_tbl); i++)
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if (dump_stdout)
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nicvf_log("%30s(%d) = 0x%" PRIx64 "\n",
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nicvf_qset_rbdr_reg_tbl[i].name, q,
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nicvf_queue_reg_read(nic,
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nicvf_qset_rbdr_reg_tbl[i].offset, q));
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else
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*data++ = nicvf_queue_reg_read(nic,
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nicvf_qset_rbdr_reg_tbl[i].offset, q);
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return 0;
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}
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int
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nicvf_reg_get_count(void)
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{
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int nr_regs;
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nr_regs = NICVF_ARRAY_SIZE(nicvf_reg_tbl);
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nr_regs += NICVF_ARRAY_SIZE(nicvf_multi_reg_tbl);
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nr_regs += NICVF_ARRAY_SIZE(nicvf_qset_cq_reg_tbl) *
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MAX_CMP_QUEUES_PER_QS;
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nr_regs += NICVF_ARRAY_SIZE(nicvf_qset_rq_reg_tbl) *
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MAX_RCV_QUEUES_PER_QS;
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nr_regs += NICVF_ARRAY_SIZE(nicvf_qset_sq_reg_tbl) *
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MAX_SND_QUEUES_PER_QS;
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nr_regs += NICVF_ARRAY_SIZE(nicvf_qset_rbdr_reg_tbl) *
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MAX_RCV_BUF_DESC_RINGS_PER_QS;
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return nr_regs;
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}
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static int
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nicvf_qset_config_internal(struct nicvf *nic, bool enable)
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{
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int ret;
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struct pf_qs_cfg pf_qs_cfg = {.value = 0};
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pf_qs_cfg.ena = enable ? 1 : 0;
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pf_qs_cfg.vnic = nic->vf_id;
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ret = nicvf_mbox_qset_config(nic, &pf_qs_cfg);
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return ret ? NICVF_ERR_SET_QS : 0;
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}
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/* Requests PF to assign and enable Qset */
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int
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nicvf_qset_config(struct nicvf *nic)
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{
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/* Enable Qset */
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return nicvf_qset_config_internal(nic, true);
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}
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int
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nicvf_qset_reclaim(struct nicvf *nic)
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{
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/* Disable Qset */
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return nicvf_qset_config_internal(nic, false);
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}
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static int
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cmpfunc(const void *a, const void *b)
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{
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return (*(const uint32_t *)a - *(const uint32_t *)b);
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}
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static uint32_t
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nicvf_roundup_list(uint32_t val, uint32_t list[], uint32_t entries)
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{
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uint32_t i;
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qsort(list, entries, sizeof(uint32_t), cmpfunc);
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for (i = 0; i < entries; i++)
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if (val <= list[i])
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break;
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/* Not in the list */
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if (i >= entries)
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return 0;
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else
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return list[i];
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}
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static void
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nicvf_handle_qset_err_intr(struct nicvf *nic)
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{
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uint16_t qidx;
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uint64_t status;
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nicvf_log("%s (VF%d)\n", __func__, nic->vf_id);
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nicvf_reg_dump(nic, NULL);
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for (qidx = 0; qidx < MAX_CMP_QUEUES_PER_QS; qidx++) {
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status = nicvf_queue_reg_read(
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nic, NIC_QSET_CQ_0_7_STATUS, qidx);
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if (!(status & NICVF_CQ_ERR_MASK))
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continue;
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if (status & NICVF_CQ_WR_FULL)
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nicvf_log("[%d]NICVF_CQ_WR_FULL\n", qidx);
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if (status & NICVF_CQ_WR_DISABLE)
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nicvf_log("[%d]NICVF_CQ_WR_DISABLE\n", qidx);
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if (status & NICVF_CQ_WR_FAULT)
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nicvf_log("[%d]NICVF_CQ_WR_FAULT\n", qidx);
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nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_STATUS, qidx, 0);
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}
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for (qidx = 0; qidx < MAX_SND_QUEUES_PER_QS; qidx++) {
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status = nicvf_queue_reg_read(
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nic, NIC_QSET_SQ_0_7_STATUS, qidx);
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if (!(status & NICVF_SQ_ERR_MASK))
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continue;
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if (status & NICVF_SQ_ERR_STOPPED)
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nicvf_log("[%d]NICVF_SQ_ERR_STOPPED\n", qidx);
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if (status & NICVF_SQ_ERR_SEND)
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nicvf_log("[%d]NICVF_SQ_ERR_SEND\n", qidx);
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if (status & NICVF_SQ_ERR_DPE)
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nicvf_log("[%d]NICVF_SQ_ERR_DPE\n", qidx);
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nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_STATUS, qidx, 0);
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}
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for (qidx = 0; qidx < MAX_RCV_BUF_DESC_RINGS_PER_QS; qidx++) {
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status = nicvf_queue_reg_read(nic,
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NIC_QSET_RBDR_0_1_STATUS0, qidx);
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status &= NICVF_RBDR_FIFO_STATE_MASK;
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status >>= NICVF_RBDR_FIFO_STATE_SHIFT;
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if (status == RBDR_FIFO_STATE_FAIL)
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nicvf_log("[%d]RBDR_FIFO_STATE_FAIL\n", qidx);
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nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx, 0);
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}
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nicvf_disable_all_interrupts(nic);
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abort();
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}
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/*
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* Handle poll mode driver interested "mbox" and "queue-set error" interrupts.
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* This function is not re-entrant.
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* The caller should provide proper serialization.
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*/
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int
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nicvf_reg_poll_interrupts(struct nicvf *nic)
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{
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int msg = 0;
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uint64_t intr;
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intr = nicvf_reg_read(nic, NIC_VF_INT);
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if (intr & NICVF_INTR_MBOX_MASK) {
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nicvf_reg_write(nic, NIC_VF_INT, NICVF_INTR_MBOX_MASK);
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msg = nicvf_handle_mbx_intr(nic);
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}
|
||||
if (intr & NICVF_INTR_QS_ERR_MASK) {
|
||||
nicvf_reg_write(nic, NIC_VF_INT, NICVF_INTR_QS_ERR_MASK);
|
||||
nicvf_handle_qset_err_intr(nic);
|
||||
}
|
||||
return msg;
|
||||
}
|
||||
|
||||
static int
|
||||
nicvf_qset_poll_reg(struct nicvf *nic, uint16_t qidx, uint32_t offset,
|
||||
uint32_t bit_pos, uint32_t bits, uint64_t val)
|
||||
{
|
||||
uint64_t bit_mask;
|
||||
uint64_t reg_val;
|
||||
int timeout = NICVF_REG_POLL_ITER_NR;
|
||||
|
||||
bit_mask = (1ULL << bits) - 1;
|
||||
bit_mask = (bit_mask << bit_pos);
|
||||
|
||||
while (timeout) {
|
||||
reg_val = nicvf_queue_reg_read(nic, offset, qidx);
|
||||
if (((reg_val & bit_mask) >> bit_pos) == val)
|
||||
return NICVF_OK;
|
||||
nicvf_delay_us(NICVF_REG_POLL_DELAY_US);
|
||||
timeout--;
|
||||
}
|
||||
return NICVF_ERR_REG_POLL;
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_rbdr_reclaim(struct nicvf *nic, uint16_t qidx)
|
||||
{
|
||||
uint64_t status;
|
||||
int timeout = NICVF_REG_POLL_ITER_NR;
|
||||
struct nicvf_rbdr *rbdr = nic->rbdr;
|
||||
|
||||
/* Save head and tail pointers for freeing up buffers */
|
||||
if (rbdr) {
|
||||
rbdr->head = nicvf_queue_reg_read(nic,
|
||||
NIC_QSET_RBDR_0_1_HEAD, qidx) >> 3;
|
||||
rbdr->tail = nicvf_queue_reg_read(nic,
|
||||
NIC_QSET_RBDR_0_1_TAIL, qidx) >> 3;
|
||||
rbdr->next_tail = rbdr->tail;
|
||||
}
|
||||
|
||||
/* Reset RBDR */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx,
|
||||
NICVF_RBDR_RESET);
|
||||
|
||||
/* Disable RBDR */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0);
|
||||
if (nicvf_qset_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0,
|
||||
62, 2, 0x00))
|
||||
return NICVF_ERR_RBDR_DISABLE;
|
||||
|
||||
while (1) {
|
||||
status = nicvf_queue_reg_read(nic,
|
||||
NIC_QSET_RBDR_0_1_PRFCH_STATUS, qidx);
|
||||
if ((status & 0xFFFFFFFF) == ((status >> 32) & 0xFFFFFFFF))
|
||||
break;
|
||||
nicvf_delay_us(NICVF_REG_POLL_DELAY_US);
|
||||
timeout--;
|
||||
if (!timeout)
|
||||
return NICVF_ERR_RBDR_PREFETCH;
|
||||
}
|
||||
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx,
|
||||
NICVF_RBDR_RESET);
|
||||
if (nicvf_qset_poll_reg(nic, qidx,
|
||||
NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x02))
|
||||
return NICVF_ERR_RBDR_RESET1;
|
||||
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0x00);
|
||||
if (nicvf_qset_poll_reg(nic, qidx,
|
||||
NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00))
|
||||
return NICVF_ERR_RBDR_RESET2;
|
||||
|
||||
return NICVF_OK;
|
||||
}
|
||||
|
||||
static int
|
||||
nicvf_qsize_regbit(uint32_t len, uint32_t len_shift)
|
||||
{
|
||||
int val;
|
||||
|
||||
val = ((uint32_t)log2(len) - len_shift);
|
||||
assert(val >= NICVF_QSIZE_MIN_VAL);
|
||||
assert(val <= NICVF_QSIZE_MAX_VAL);
|
||||
return val;
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_rbdr_config(struct nicvf *nic, uint16_t qidx)
|
||||
{
|
||||
int ret;
|
||||
uint64_t head, tail;
|
||||
struct nicvf_rbdr *rbdr = nic->rbdr;
|
||||
struct rbdr_cfg rbdr_cfg = {.value = 0};
|
||||
|
||||
ret = nicvf_qset_rbdr_reclaim(nic, qidx);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Set descriptor base address */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_BASE, qidx, rbdr->phys);
|
||||
|
||||
/* Enable RBDR & set queue size */
|
||||
rbdr_cfg.ena = 1;
|
||||
rbdr_cfg.reset = 0;
|
||||
rbdr_cfg.ldwb = 0;
|
||||
rbdr_cfg.qsize = nicvf_qsize_regbit(rbdr->qlen_mask + 1,
|
||||
RBDR_SIZE_SHIFT);
|
||||
rbdr_cfg.avg_con = 0;
|
||||
rbdr_cfg.lines = rbdr->buffsz / 128;
|
||||
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, rbdr_cfg.value);
|
||||
|
||||
/* Verify proper RBDR reset */
|
||||
head = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_HEAD, qidx);
|
||||
tail = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, qidx);
|
||||
|
||||
if (head | tail)
|
||||
return NICVF_ERR_RBDR_RESET;
|
||||
|
||||
return NICVF_OK;
|
||||
}
|
||||
|
||||
uint32_t
|
||||
nicvf_qsize_rbdr_roundup(uint32_t val)
|
||||
{
|
||||
uint32_t list[] = {RBDR_QUEUE_SZ_8K, RBDR_QUEUE_SZ_16K,
|
||||
RBDR_QUEUE_SZ_32K, RBDR_QUEUE_SZ_64K,
|
||||
RBDR_QUEUE_SZ_128K, RBDR_QUEUE_SZ_256K,
|
||||
RBDR_QUEUE_SZ_512K};
|
||||
return nicvf_roundup_list(val, list, NICVF_ARRAY_SIZE(list));
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_rbdr_precharge(struct nicvf *nic, uint16_t ridx,
|
||||
rbdr_pool_get_handler handler,
|
||||
void *opaque, uint32_t max_buffs)
|
||||
{
|
||||
struct rbdr_entry_t *desc, *desc0;
|
||||
struct nicvf_rbdr *rbdr = nic->rbdr;
|
||||
uint32_t count;
|
||||
nicvf_phys_addr_t phy;
|
||||
|
||||
assert(rbdr != NULL);
|
||||
desc = rbdr->desc;
|
||||
count = 0;
|
||||
/* Don't fill beyond max numbers of desc */
|
||||
while (count < rbdr->qlen_mask) {
|
||||
if (count >= max_buffs)
|
||||
break;
|
||||
desc0 = desc + count;
|
||||
phy = handler(opaque);
|
||||
if (phy) {
|
||||
desc0->full_addr = phy;
|
||||
count++;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
nicvf_smp_wmb();
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR, ridx, count);
|
||||
rbdr->tail = nicvf_queue_reg_read(nic,
|
||||
NIC_QSET_RBDR_0_1_TAIL, ridx) >> 3;
|
||||
rbdr->next_tail = rbdr->tail;
|
||||
nicvf_smp_rmb();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_rbdr_active(struct nicvf *nic, uint16_t qidx)
|
||||
{
|
||||
return nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx);
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_sq_reclaim(struct nicvf *nic, uint16_t qidx)
|
||||
{
|
||||
uint64_t head, tail;
|
||||
struct sq_cfg sq_cfg;
|
||||
|
||||
sq_cfg.value = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx);
|
||||
|
||||
/* Disable send queue */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, 0);
|
||||
|
||||
/* Check if SQ is stopped */
|
||||
if (sq_cfg.ena && nicvf_qset_poll_reg(nic, qidx, NIC_QSET_SQ_0_7_STATUS,
|
||||
NICVF_SQ_STATUS_STOPPED_BIT, 1, 0x01))
|
||||
return NICVF_ERR_SQ_DISABLE;
|
||||
|
||||
/* Reset send queue */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET);
|
||||
head = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_HEAD, qidx) >> 4;
|
||||
tail = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_TAIL, qidx) >> 4;
|
||||
if (head | tail)
|
||||
return NICVF_ERR_SQ_RESET;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_sq_config(struct nicvf *nic, uint16_t qidx, struct nicvf_txq *txq)
|
||||
{
|
||||
int ret;
|
||||
struct sq_cfg sq_cfg = {.value = 0};
|
||||
|
||||
ret = nicvf_qset_sq_reclaim(nic, qidx);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Send a mailbox msg to PF to config SQ */
|
||||
if (nicvf_mbox_sq_config(nic, qidx))
|
||||
return NICVF_ERR_SQ_PF_CFG;
|
||||
|
||||
/* Set queue base address */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE, qidx, txq->phys);
|
||||
|
||||
/* Enable send queue & set queue size */
|
||||
sq_cfg.ena = 1;
|
||||
sq_cfg.reset = 0;
|
||||
sq_cfg.ldwb = 0;
|
||||
sq_cfg.qsize = nicvf_qsize_regbit(txq->qlen_mask + 1, SND_QSIZE_SHIFT);
|
||||
sq_cfg.tstmp_bgx_intf = 0;
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg.value);
|
||||
|
||||
/* Ring doorbell so that H/W restarts processing SQEs */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, qidx, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t
|
||||
nicvf_qsize_sq_roundup(uint32_t val)
|
||||
{
|
||||
uint32_t list[] = {SND_QUEUE_SZ_1K, SND_QUEUE_SZ_2K,
|
||||
SND_QUEUE_SZ_4K, SND_QUEUE_SZ_8K,
|
||||
SND_QUEUE_SZ_16K, SND_QUEUE_SZ_32K,
|
||||
SND_QUEUE_SZ_64K};
|
||||
return nicvf_roundup_list(val, list, NICVF_ARRAY_SIZE(list));
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_rq_reclaim(struct nicvf *nic, uint16_t qidx)
|
||||
{
|
||||
/* Disable receive queue */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, 0);
|
||||
return nicvf_mbox_rq_sync(nic);
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_rq_config(struct nicvf *nic, uint16_t qidx, struct nicvf_rxq *rxq)
|
||||
{
|
||||
struct pf_rq_cfg pf_rq_cfg = {.value = 0};
|
||||
struct rq_cfg rq_cfg = {.value = 0};
|
||||
|
||||
if (nicvf_qset_rq_reclaim(nic, qidx))
|
||||
return NICVF_ERR_RQ_CLAIM;
|
||||
|
||||
pf_rq_cfg.strip_pre_l2 = 0;
|
||||
/* First cache line of RBDR data will be allocated into L2C */
|
||||
pf_rq_cfg.caching = RQ_CACHE_ALLOC_FIRST;
|
||||
pf_rq_cfg.cq_qs = nic->vf_id;
|
||||
pf_rq_cfg.cq_idx = qidx;
|
||||
pf_rq_cfg.rbdr_cont_qs = nic->vf_id;
|
||||
pf_rq_cfg.rbdr_cont_idx = 0;
|
||||
pf_rq_cfg.rbdr_strt_qs = nic->vf_id;
|
||||
pf_rq_cfg.rbdr_strt_idx = 0;
|
||||
|
||||
/* Send a mailbox msg to PF to config RQ */
|
||||
if (nicvf_mbox_rq_config(nic, qidx, &pf_rq_cfg))
|
||||
return NICVF_ERR_RQ_PF_CFG;
|
||||
|
||||
/* Select Rx backpressure */
|
||||
if (nicvf_mbox_rq_bp_config(nic, qidx, rxq->rx_drop_en))
|
||||
return NICVF_ERR_RQ_BP_CFG;
|
||||
|
||||
/* Send a mailbox msg to PF to config RQ drop */
|
||||
if (nicvf_mbox_rq_drop_config(nic, qidx, rxq->rx_drop_en))
|
||||
return NICVF_ERR_RQ_DROP_CFG;
|
||||
|
||||
/* Enable Receive queue */
|
||||
rq_cfg.ena = 1;
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, rq_cfg.value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_cq_reclaim(struct nicvf *nic, uint16_t qidx)
|
||||
{
|
||||
uint64_t tail, head;
|
||||
|
||||
/* Disable completion queue */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, 0);
|
||||
if (nicvf_qset_poll_reg(nic, qidx, NIC_QSET_CQ_0_7_CFG, 42, 1, 0))
|
||||
return NICVF_ERR_CQ_DISABLE;
|
||||
|
||||
/* Reset completion queue */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET);
|
||||
tail = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_TAIL, qidx) >> 9;
|
||||
head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, qidx) >> 9;
|
||||
if (head | tail)
|
||||
return NICVF_ERR_CQ_RESET;
|
||||
|
||||
/* Disable timer threshold (doesn't get reset upon CQ reset) */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_qset_cq_config(struct nicvf *nic, uint16_t qidx, struct nicvf_rxq *rxq)
|
||||
{
|
||||
int ret;
|
||||
struct cq_cfg cq_cfg = {.value = 0};
|
||||
|
||||
ret = nicvf_qset_cq_reclaim(nic, qidx);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Set completion queue base address */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_BASE, qidx, rxq->phys);
|
||||
|
||||
cq_cfg.ena = 1;
|
||||
cq_cfg.reset = 0;
|
||||
/* Writes of CQE will be allocated into L2C */
|
||||
cq_cfg.caching = 1;
|
||||
cq_cfg.qsize = nicvf_qsize_regbit(rxq->qlen_mask + 1, CMP_QSIZE_SHIFT);
|
||||
cq_cfg.avg_con = 0;
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, cq_cfg.value);
|
||||
|
||||
/* Set threshold value for interrupt generation */
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_THRESH, qidx, 0);
|
||||
nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t
|
||||
nicvf_qsize_cq_roundup(uint32_t val)
|
||||
{
|
||||
uint32_t list[] = {CMP_QUEUE_SZ_1K, CMP_QUEUE_SZ_2K,
|
||||
CMP_QUEUE_SZ_4K, CMP_QUEUE_SZ_8K,
|
||||
CMP_QUEUE_SZ_16K, CMP_QUEUE_SZ_32K,
|
||||
CMP_QUEUE_SZ_64K};
|
||||
return nicvf_roundup_list(val, list, NICVF_ARRAY_SIZE(list));
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
nicvf_vlan_hw_strip(struct nicvf *nic, bool enable)
|
||||
{
|
||||
uint64_t val;
|
||||
|
||||
val = nicvf_reg_read(nic, NIC_VNIC_RQ_GEN_CFG);
|
||||
if (enable)
|
||||
val |= (STRIP_FIRST_VLAN << 25);
|
||||
else
|
||||
val &= ~((STRIP_SECOND_VLAN | STRIP_FIRST_VLAN) << 25);
|
||||
|
||||
nicvf_reg_write(nic, NIC_VNIC_RQ_GEN_CFG, val);
|
||||
}
|
||||
|
||||
int
|
||||
nicvf_loopback_config(struct nicvf *nic, bool enable)
|
||||
{
|
||||
if (enable && nic->loopback_supported == 0)
|
||||
return NICVF_ERR_LOOPBACK_CFG;
|
||||
|
||||
return nicvf_mbox_loopback_config(nic, enable);
|
||||
}
|
||||
176
drivers/net/thunderx/base/nicvf_hw.h
Normal file
176
drivers/net/thunderx/base/nicvf_hw.h
Normal file
@ -0,0 +1,176 @@
|
||||
/*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright (C) Cavium networks Ltd. 2016.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Cavium networks nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _THUNDERX_NICVF_HW_H
|
||||
#define _THUNDERX_NICVF_HW_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nicvf_hw_defs.h"
|
||||
|
||||
#define PCI_VENDOR_ID_CAVIUM 0x177D
|
||||
#define PCI_DEVICE_ID_THUNDERX_PASS1_NICVF 0x0011
|
||||
#define PCI_DEVICE_ID_THUNDERX_PASS2_NICVF 0xA034
|
||||
#define PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF 0xA11E
|
||||
#define PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF 0xA134
|
||||
|
||||
#define NICVF_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
|
||||
|
||||
#define NICVF_PASS1 (PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF)
|
||||
#define NICVF_PASS2 (PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF)
|
||||
|
||||
#define NICVF_CAP_TUNNEL_PARSING (1ULL << 0)
|
||||
|
||||
enum nicvf_tns_mode {
|
||||
NIC_TNS_BYPASS_MODE,
|
||||
NIC_TNS_MODE,
|
||||
};
|
||||
|
||||
enum nicvf_err_e {
|
||||
NICVF_OK,
|
||||
NICVF_ERR_SET_QS = -8191,/* -8191 */
|
||||
NICVF_ERR_RESET_QS, /* -8190 */
|
||||
NICVF_ERR_REG_POLL, /* -8189 */
|
||||
NICVF_ERR_RBDR_RESET, /* -8188 */
|
||||
NICVF_ERR_RBDR_DISABLE, /* -8187 */
|
||||
NICVF_ERR_RBDR_PREFETCH, /* -8186 */
|
||||
NICVF_ERR_RBDR_RESET1, /* -8185 */
|
||||
NICVF_ERR_RBDR_RESET2, /* -8184 */
|
||||
NICVF_ERR_RQ_CLAIM, /* -8183 */
|
||||
NICVF_ERR_RQ_PF_CFG, /* -8182 */
|
||||
NICVF_ERR_RQ_BP_CFG, /* -8181 */
|
||||
NICVF_ERR_RQ_DROP_CFG, /* -8180 */
|
||||
NICVF_ERR_CQ_DISABLE, /* -8179 */
|
||||
NICVF_ERR_CQ_RESET, /* -8178 */
|
||||
NICVF_ERR_SQ_DISABLE, /* -8177 */
|
||||
NICVF_ERR_SQ_RESET, /* -8176 */
|
||||
NICVF_ERR_SQ_PF_CFG, /* -8175 */
|
||||
NICVF_ERR_LOOPBACK_CFG, /* -8174 */
|
||||
NICVF_ERR_BASE_INIT, /* -8173 */
|
||||
};
|
||||
|
||||
typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *opaque);
|
||||
|
||||
/* Common structs used in DPDK and base layer are defined in DPDK layer */
|
||||
#include "../nicvf_struct.h"
|
||||
|
||||
NICVF_STATIC_ASSERT(sizeof(struct nicvf_rbdr) <= 128);
|
||||
NICVF_STATIC_ASSERT(sizeof(struct nicvf_txq) <= 128);
|
||||
NICVF_STATIC_ASSERT(sizeof(struct nicvf_rxq) <= 128);
|
||||
|
||||
static inline void
|
||||
nicvf_reg_write(struct nicvf *nic, uint32_t offset, uint64_t val)
|
||||
{
|
||||
nicvf_addr_write(nic->reg_base + offset, val);
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
nicvf_reg_read(struct nicvf *nic, uint32_t offset)
|
||||
{
|
||||
return nicvf_addr_read(nic->reg_base + offset);
|
||||
}
|
||||
|
||||
static inline uintptr_t
|
||||
nicvf_qset_base(struct nicvf *nic, uint32_t qidx)
|
||||
{
|
||||
return nic->reg_base + (qidx << NIC_Q_NUM_SHIFT);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nicvf_queue_reg_write(struct nicvf *nic, uint32_t offset, uint32_t qidx,
|
||||
uint64_t val)
|
||||
{
|
||||
nicvf_addr_write(nicvf_qset_base(nic, qidx) + offset, val);
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
nicvf_queue_reg_read(struct nicvf *nic, uint32_t offset, uint32_t qidx)
|
||||
{
|
||||
return nicvf_addr_read(nicvf_qset_base(nic, qidx) + offset);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nicvf_disable_all_interrupts(struct nicvf *nic)
|
||||
{
|
||||
nicvf_reg_write(nic, NIC_VF_ENA_W1C, NICVF_INTR_ALL_MASK);
|
||||
nicvf_reg_write(nic, NIC_VF_INT, NICVF_INTR_ALL_MASK);
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
nicvf_hw_version(struct nicvf *nic)
|
||||
{
|
||||
return nic->subsystem_device_id;
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
nicvf_hw_cap(struct nicvf *nic)
|
||||
{
|
||||
return nic->hwcap;
|
||||
}
|
||||
|
||||
int nicvf_base_init(struct nicvf *nic);
|
||||
|
||||
int nicvf_reg_get_count(void);
|
||||
int nicvf_reg_poll_interrupts(struct nicvf *nic);
|
||||
int nicvf_reg_dump(struct nicvf *nic, uint64_t *data);
|
||||
|
||||
int nicvf_qset_config(struct nicvf *nic);
|
||||
int nicvf_qset_reclaim(struct nicvf *nic);
|
||||
|
||||
int nicvf_qset_rbdr_config(struct nicvf *nic, uint16_t qidx);
|
||||
int nicvf_qset_rbdr_reclaim(struct nicvf *nic, uint16_t qidx);
|
||||
int nicvf_qset_rbdr_precharge(struct nicvf *nic, uint16_t ridx,
|
||||
rbdr_pool_get_handler handler, void *opaque,
|
||||
uint32_t max_buffs);
|
||||
int nicvf_qset_rbdr_active(struct nicvf *nic, uint16_t qidx);
|
||||
|
||||
int nicvf_qset_rq_config(struct nicvf *nic, uint16_t qidx,
|
||||
struct nicvf_rxq *rxq);
|
||||
int nicvf_qset_rq_reclaim(struct nicvf *nic, uint16_t qidx);
|
||||
|
||||
int nicvf_qset_cq_config(struct nicvf *nic, uint16_t qidx,
|
||||
struct nicvf_rxq *rxq);
|
||||
int nicvf_qset_cq_reclaim(struct nicvf *nic, uint16_t qidx);
|
||||
|
||||
int nicvf_qset_sq_config(struct nicvf *nic, uint16_t qidx,
|
||||
struct nicvf_txq *txq);
|
||||
int nicvf_qset_sq_reclaim(struct nicvf *nic, uint16_t qidx);
|
||||
|
||||
uint32_t nicvf_qsize_rbdr_roundup(uint32_t val);
|
||||
uint32_t nicvf_qsize_cq_roundup(uint32_t val);
|
||||
uint32_t nicvf_qsize_sq_roundup(uint32_t val);
|
||||
|
||||
void nicvf_vlan_hw_strip(struct nicvf *nic, bool enable);
|
||||
|
||||
int nicvf_loopback_config(struct nicvf *nic, bool enable);
|
||||
|
||||
#endif /* _THUNDERX_NICVF_HW_H */
|
||||
@ -126,6 +126,7 @@ do { \
|
||||
|
||||
#endif
|
||||
|
||||
#include "nicvf_hw.h"
|
||||
#include "nicvf_mbox.h"
|
||||
|
||||
#endif /* _THUNDERX_NICVF_H */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user