d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

vdpa/mlx5: specify lag port affinity

Browse Source 
If set TIS lag port affinity to auto, firmware assign port affinity on
each creation with Round Robin. In case of 2 PFs, if create virtq,
destroy and create again, then each virtq will get same port affinity.

To resolve this fw limitation, this patch sets create TIS with specified
affinity for each PF.

Fixes: bff735011078 ("vdpa/mlx5: prepare virtio queues")
Cc: stable@dpdk.org

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
This commit is contained in:
Xueming Li 2020-10-28 10:44:39 +00:00 committed by Ferruh Yigit
parent 1cbdad1bf2
commit c783fd433c
3 changed files with 19 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/vdpa/mlx5/mlx5_vdpa.c
View File

@ -732,6 +732,9 @@ mlx5_vdpa_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
}
priv->caps = attr.vdpa;
priv->log_max_rqt_size = attr.log_max_rqt_size;
priv->num_lag_ports = attr.num_lag_ports;
if (attr.num_lag_ports == 0)
priv->num_lag_ports = 1;
priv->ctx = ctx;
priv->pci_dev = pci_dev;
priv->var = mlx5_glue->dv_alloc_var(ctx, 0);

3
drivers/vdpa/mlx5/mlx5_vdpa.h
View File

@ -151,8 +151,9 @@ struct mlx5_vdpa_priv {
struct rte_intr_handle intr_handle;
struct rte_intr_handle err_intr_handle;
struct mlx5_devx_obj *td;
struct mlx5_devx_obj *tis;
struct mlx5_devx_obj *tiss[16]; /* TIS list for each LAG port. */
uint16_t nr_virtqs;
uint8_t num_lag_ports;
uint64_t features; /* Negotiated features. */
uint16_t log_max_rqt_size;
struct mlx5_vdpa_steer steer;

22
drivers/vdpa/mlx5/mlx5_vdpa_virtq.c
View File

@ -111,9 +111,11 @@ mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv)
memset(virtq->err_time, 0, sizeof(virtq->err_time));
virtq->n_retry = 0;
}
if (priv->tis) {
claim_zero(mlx5_devx_cmd_destroy(priv->tis));
priv->tis = NULL;
for (i = 0; i < priv->num_lag_ports; i++) {
if (priv->tiss[i]) {
claim_zero(mlx5_devx_cmd_destroy(priv->tiss[i]));
priv->tiss[i] = NULL;
}
}
if (priv->td) {
claim_zero(mlx5_devx_cmd_destroy(priv->td));
@ -322,7 +324,7 @@ mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index)
attr.hw_used_index = last_used_idx;
attr.q_size = vq.size;
attr.mkey = priv->gpa_mkey_index;
attr.tis_id = priv->tis->id;
attr.tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id;
attr.queue_index = index;
attr.pd = priv->pdn;
virtq->virtq = mlx5_devx_cmd_create_virtq(priv->ctx, &attr);
@ -465,10 +467,14 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv)
return -rte_errno;
}
tis_attr.transport_domain = priv->td->id;
priv->tis = mlx5_devx_cmd_create_tis(priv->ctx, &tis_attr);
if (!priv->tis) {
DRV_LOG(ERR, "Failed to create TIS.");
goto error;
for (i = 0; i < priv->num_lag_ports; i++) {
/* 0 is auto affinity, non-zero value to propose port. */
tis_attr.lag_tx_port_affinity = i + 1;
priv->tiss[i] = mlx5_devx_cmd_create_tis(priv->ctx, &tis_attr);
if (!priv->tiss[i]) {
DRV_LOG(ERR, "Failed to create TIS %u.", i);
goto error;
}
}
priv->nr_virtqs = nr_vring;
for (i = 0; i < nr_vring; i++)