net/sfc: support more options for a number of Tx descriptors
The number of Tx descriptors is not used as HW Tx ring size any more. It simply defines maximum fill level. Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com> Reviewed-by: Andy Moreton <amoreton@solarflare.com>
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@ -79,6 +79,13 @@ struct sfc_dp_tx_qcreate_info {
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volatile void *mem_bar;
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};
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/**
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* Get Tx datapath specific device info.
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*
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* @param dev_info Device info to be adjusted
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*/
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typedef void (sfc_dp_tx_get_dev_info_t)(struct rte_eth_dev_info *dev_info);
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/**
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* Get size of transmit and event queue rings by the number of Tx
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* descriptors.
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@ -162,6 +169,7 @@ struct sfc_dp_tx {
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#define SFC_DP_TX_FEAT_MULTI_PROCESS 0x8
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#define SFC_DP_TX_FEAT_MULTI_POOL 0x10
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#define SFC_DP_TX_FEAT_REFCNT 0x20
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sfc_dp_tx_get_dev_info_t *get_dev_info;
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sfc_dp_tx_qsize_up_rings_t *qsize_up_rings;
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sfc_dp_tx_qcreate_t *qcreate;
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sfc_dp_tx_qdestroy_t *qdestroy;
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@ -481,6 +481,17 @@ sfc_ef10_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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return pktp - &tx_pkts[0];
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}
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static sfc_dp_tx_get_dev_info_t sfc_ef10_get_dev_info;
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static void
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sfc_ef10_get_dev_info(struct rte_eth_dev_info *dev_info)
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{
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/*
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* Number of descriptors just defines maximum number of pushed
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* descriptors (fill level).
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*/
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dev_info->tx_desc_lim.nb_min = 1;
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dev_info->tx_desc_lim.nb_align = 1;
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}
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static sfc_dp_tx_qsize_up_rings_t sfc_ef10_tx_qsize_up_rings;
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static int
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@ -489,9 +500,19 @@ sfc_ef10_tx_qsize_up_rings(uint16_t nb_tx_desc,
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unsigned int *evq_entries,
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unsigned int *txq_max_fill_level)
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{
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*txq_entries = nb_tx_desc;
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*evq_entries = nb_tx_desc;
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*txq_max_fill_level = SFC_EF10_TXQ_LIMIT(*txq_entries);
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/*
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* rte_ethdev API guarantees that the number meets min, max and
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* alignment requirements.
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*/
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if (nb_tx_desc <= EFX_TXQ_MINNDESCS)
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*txq_entries = EFX_TXQ_MINNDESCS;
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else
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*txq_entries = rte_align32pow2(nb_tx_desc);
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*evq_entries = *txq_entries;
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*txq_max_fill_level = RTE_MIN(nb_tx_desc,
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SFC_EF10_TXQ_LIMIT(*evq_entries));
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return 0;
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}
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@ -637,6 +658,7 @@ struct sfc_dp_tx sfc_ef10_tx = {
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SFC_DP_TX_FEAT_MULTI_POOL |
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SFC_DP_TX_FEAT_REFCNT |
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SFC_DP_TX_FEAT_MULTI_PROCESS,
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.get_dev_info = sfc_ef10_get_dev_info,
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.qsize_up_rings = sfc_ef10_tx_qsize_up_rings,
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.qcreate = sfc_ef10_tx_qcreate,
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.qdestroy = sfc_ef10_tx_qdestroy,
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@ -654,6 +676,7 @@ struct sfc_dp_tx sfc_ef10_simple_tx = {
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.type = SFC_DP_TX,
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},
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.features = SFC_DP_TX_FEAT_MULTI_PROCESS,
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.get_dev_info = sfc_ef10_get_dev_info,
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.qsize_up_rings = sfc_ef10_tx_qsize_up_rings,
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.qcreate = sfc_ef10_tx_qcreate,
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.qdestroy = sfc_ef10_tx_qdestroy,
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@ -178,6 +178,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
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*/
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dev_info->rx_desc_lim.nb_align = EFX_RXQ_MINNDESCS;
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/* Initialize to hardware limits */
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dev_info->tx_desc_lim.nb_max = sa->txq_max_entries;
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dev_info->tx_desc_lim.nb_min = EFX_TXQ_MINNDESCS;
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/*
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@ -188,6 +189,8 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
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if (sa->dp_rx->get_dev_info != NULL)
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sa->dp_rx->get_dev_info(dev_info);
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if (sa->dp_tx->get_dev_info != NULL)
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sa->dp_tx->get_dev_info(dev_info);
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}
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static const uint32_t *
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@ -160,6 +160,10 @@ sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
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&txq_max_fill_level);
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if (rc != 0)
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goto fail_size_up_rings;
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SFC_ASSERT(txq_entries >= EFX_TXQ_MINNDESCS);
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SFC_ASSERT(txq_entries <= sa->txq_max_entries);
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SFC_ASSERT(txq_entries >= nb_tx_desc);
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SFC_ASSERT(txq_max_fill_level <= nb_tx_desc);
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rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf);
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if (rc != 0)
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@ -168,7 +172,6 @@ sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
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SFC_ASSERT(sw_index < sa->txq_count);
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txq_info = &sa->txq_info[sw_index];
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SFC_ASSERT(txq_entries <= sa->txq_max_entries);
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txq_info->entries = txq_entries;
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rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index,
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