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net/ngbe: fix debug logs

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Remove 'DEBUGFUNC' due to too many invalid debug log prints, unify the
DEBUG level macros.

Fixes: cc934df178 ("net/ngbe: add log and error types")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
This commit is contained in:
Jiawen Wu 2022-02-23 18:28:56 +08:00 committed by Ferruh Yigit
parent dffc3e9be3
commit c811e6a492
9 changed files with 65 additions and 237 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/net/ngbe/base/ngbe_eeprom.c
View File

@ -20,8 +20,6 @@ s32 ngbe_init_eeprom_params(struct ngbe_hw *hw)
u32 eec;
u16 eeprom_size;
DEBUGFUNC("ngbe_init_eeprom_params");
if (eeprom->type != ngbe_eeprom_unknown)
return 0;
@ -52,8 +50,8 @@ s32 ngbe_init_eeprom_params(struct ngbe_hw *hw)
eeprom->address_bits = 16;
eeprom->sw_addr = 0x80;
DEBUGOUT("eeprom params: type = %d, size = %d, address bits: "
"%d %d\n", eeprom->type, eeprom->word_size,
DEBUGOUT("eeprom params: type = %d, size = %d, address bits: %d %d",
eeprom->type, eeprom->word_size,
eeprom->address_bits, eeprom->sw_addr);
return 0;
@ -72,9 +70,6 @@ s32 ngbe_get_eeprom_semaphore(struct ngbe_hw *hw)
u32 i;
u32 swsm;
DEBUGFUNC("ngbe_get_eeprom_semaphore");
/* Get SMBI software semaphore between device drivers first */
for (i = 0; i < timeout; i++) {
/*
@ -90,8 +85,7 @@ s32 ngbe_get_eeprom_semaphore(struct ngbe_hw *hw)
}
if (i == timeout) {
DEBUGOUT("Driver can't access the eeprom - SMBI Semaphore "
"not granted.\n");
DEBUGOUT("Driver can't access the eeprom - SMBI Semaphore not granted.");
/*
* this release is particularly important because our attempts
* above to get the semaphore may have succeeded, and if there
@ -134,13 +128,12 @@ s32 ngbe_get_eeprom_semaphore(struct ngbe_hw *hw)
* was not granted because we don't have access to the EEPROM
*/
if (i >= timeout) {
DEBUGOUT("SWESMBI Software EEPROM semaphore not granted.\n");
DEBUGOUT("SWESMBI Software EEPROM semaphore not granted.");
ngbe_release_eeprom_semaphore(hw);
status = NGBE_ERR_EEPROM;
}
} else {
DEBUGOUT("Software semaphore SMBI between device drivers "
"not granted.\n");
DEBUGOUT("Software semaphore SMBI between device drivers not granted.");
}
return status;
@ -154,8 +147,6 @@ s32 ngbe_get_eeprom_semaphore(struct ngbe_hw *hw)
**/
void ngbe_release_eeprom_semaphore(struct ngbe_hw *hw)
{
DEBUGFUNC("ngbe_release_eeprom_semaphore");
wr32m(hw, NGBE_MNGSWSYNC, NGBE_MNGSWSYNC_REQ, 0);
wr32m(hw, NGBE_SWSEM, NGBE_SWSEM_PF, 0);
ngbe_flush(hw);
@ -276,7 +267,6 @@ s32 ngbe_validate_eeprom_checksum_em(struct ngbe_hw *hw,
u32 eeprom_cksum_devcap = 0;
int err = 0;
DEBUGFUNC("ngbe_validate_eeprom_checksum_em");
UNREFERENCED_PARAMETER(checksum_val);
/* Check EEPROM only once */
@ -315,8 +305,6 @@ s32 ngbe_save_eeprom_version(struct ngbe_hw *hw)
u32 etrack_id = 0;
u32 offset = (hw->rom.sw_addr + NGBE_EEPROM_VERSION_L) << 1;
DEBUGFUNC("ngbe_save_eeprom_version");
if (hw->bus.lan_id == 0) {
hw->rom.read32(hw, offset, &eeprom_verl);
etrack_id = eeprom_verl;

152
drivers/net/ngbe/base/ngbe_hw.c
View File

@ -20,8 +20,6 @@ s32 ngbe_start_hw(struct ngbe_hw *hw)
{
s32 err;
DEBUGFUNC("ngbe_start_hw");
/* Clear the VLAN filter table */
hw->mac.clear_vfta(hw);
@ -31,7 +29,7 @@ s32 ngbe_start_hw(struct ngbe_hw *hw)
/* Setup flow control */
err = hw->mac.setup_fc(hw);
if (err != 0 && err != NGBE_NOT_IMPLEMENTED) {
DEBUGOUT("Flow control setup failed, returning %d\n", err);
DEBUGOUT("Flow control setup failed, returning %d", err);
return err;
}
@ -55,8 +53,6 @@ s32 ngbe_init_hw(struct ngbe_hw *hw)
{
s32 status;
DEBUGFUNC("ngbe_init_hw");
ngbe_save_eeprom_version(hw);
/* Reset the hardware */
@ -67,7 +63,7 @@ s32 ngbe_init_hw(struct ngbe_hw *hw)
}
if (status != 0)
DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
DEBUGOUT("Failed to initialize HW, STATUS = %d", status);
return status;
}
@ -155,8 +151,6 @@ s32 ngbe_reset_hw_em(struct ngbe_hw *hw)
{
s32 status;
DEBUGFUNC("ngbe_reset_hw_em");
/* Call adapter stop to disable tx/rx and clear interrupts */
status = hw->mac.stop_hw(hw);
if (status != 0)
@ -204,8 +198,6 @@ s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw)
{
u16 i = 0;
DEBUGFUNC("ngbe_clear_hw_cntrs");
/* QP Stats */
/* don't write clear queue stats */
for (i = 0; i < NGBE_MAX_QP; i++) {
@ -304,8 +296,6 @@ s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr)
u32 rar_low;
u16 i;
DEBUGFUNC("ngbe_get_mac_addr");
wr32(hw, NGBE_ETHADDRIDX, 0);
rar_high = rd32(hw, NGBE_ETHADDRH);
rar_low = rd32(hw, NGBE_ETHADDRL);
@ -331,8 +321,6 @@ void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)
struct ngbe_bus_info *bus = &hw->bus;
u32 reg = 0;
DEBUGFUNC("ngbe_set_lan_id_multi_port");
reg = rd32(hw, NGBE_PORTSTAT);
bus->lan_id = NGBE_PORTSTAT_ID(reg);
bus->func = bus->lan_id;
@ -352,8 +340,6 @@ s32 ngbe_stop_hw(struct ngbe_hw *hw)
u16 i;
s32 status = 0;
DEBUGFUNC("ngbe_stop_hw");
/*
* Set the adapter_stopped flag so other driver functions stop touching
* the hardware
@ -409,8 +395,6 @@ s32 ngbe_led_on(struct ngbe_hw *hw, u32 index)
{
u32 led_reg = rd32(hw, NGBE_LEDCTL);
DEBUGFUNC("ngbe_led_on");
if (index > 3)
return NGBE_ERR_PARAM;
@ -431,8 +415,6 @@ s32 ngbe_led_off(struct ngbe_hw *hw, u32 index)
{
u32 led_reg = rd32(hw, NGBE_LEDCTL);
DEBUGFUNC("ngbe_led_off");
if (index > 3)
return NGBE_ERR_PARAM;
@ -454,8 +436,6 @@ s32 ngbe_validate_mac_addr(u8 *mac_addr)
{
s32 status = 0;
DEBUGFUNC("ngbe_validate_mac_addr");
/* Make sure it is not a multicast address */
if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) {
status = NGBE_ERR_INVALID_MAC_ADDR;
@ -486,11 +466,9 @@ s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
u32 rar_low, rar_high;
u32 rar_entries = hw->mac.num_rar_entries;
DEBUGFUNC("ngbe_set_rar");
/* Make sure we are using a valid rar index range */
if (index >= rar_entries) {
DEBUGOUT("RAR index %d is out of range.\n", index);
DEBUGOUT("RAR index %d is out of range.", index);
return NGBE_ERR_INVALID_ARGUMENT;
}
@ -538,11 +516,9 @@ s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index)
u32 rar_high;
u32 rar_entries = hw->mac.num_rar_entries;
DEBUGFUNC("ngbe_clear_rar");
/* Make sure we are using a valid rar index range */
if (index >= rar_entries) {
DEBUGOUT("RAR index %d is out of range.\n", index);
DEBUGOUT("RAR index %d is out of range.", index);
return NGBE_ERR_INVALID_ARGUMENT;
}
@ -578,8 +554,6 @@ s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
u32 psrctl;
u32 rar_entries = hw->mac.num_rar_entries;
DEBUGFUNC("ngbe_init_rx_addrs");
/*
* If the current mac address is valid, assume it is a software override
* to the permanent address.
@ -590,18 +564,18 @@ s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
/* Get the MAC address from the RAR0 for later reference */
hw->mac.get_mac_addr(hw, hw->mac.addr);
DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
DEBUGOUT(" Keeping Current RAR0 Addr = "
RTE_ETHER_ADDR_PRT_FMT,
hw->mac.addr[0], hw->mac.addr[1],
hw->mac.addr[2]);
DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
hw->mac.addr[2], hw->mac.addr[3],
hw->mac.addr[4], hw->mac.addr[5]);
} else {
/* Setup the receive address. */
DEBUGOUT("Overriding MAC Address in RAR[0]\n");
DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
DEBUGOUT("Overriding MAC Address in RAR[0]");
DEBUGOUT(" New MAC Addr = "
RTE_ETHER_ADDR_PRT_FMT,
hw->mac.addr[0], hw->mac.addr[1],
hw->mac.addr[2]);
DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
hw->mac.addr[2], hw->mac.addr[3],
hw->mac.addr[4], hw->mac.addr[5]);
hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
@ -611,7 +585,7 @@ s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
/* Zero out the other receive addresses. */
DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
DEBUGOUT("Clearing RAR[1-%d]", rar_entries - 1);
for (i = 1; i < rar_entries; i++) {
wr32(hw, NGBE_ETHADDRIDX, i);
wr32(hw, NGBE_ETHADDRL, 0);
@ -625,7 +599,7 @@ s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
wr32(hw, NGBE_PSRCTL, psrctl);
DEBUGOUT(" Clearing MTA\n");
DEBUGOUT(" Clearing MTA");
for (i = 0; i < hw->mac.mcft_size; i++)
wr32(hw, NGBE_MCADDRTBL(i), 0);
@ -650,8 +624,6 @@ static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr)
{
u32 vector = 0;
DEBUGFUNC("ngbe_mta_vector");
switch (hw->mac.mc_filter_type) {
case 0: /* use bits [47:36] of the address */
vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
@ -666,7 +638,7 @@ static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr)
vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
break;
default: /* Invalid mc_filter_type */
DEBUGOUT("MC filter type param set incorrectly\n");
DEBUGOUT("MC filter type param set incorrectly");
ASSERT(0);
break;
}
@ -689,12 +661,10 @@ void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr)
u32 vector_bit;
u32 vector_reg;
DEBUGFUNC("ngbe_set_mta");
hw->addr_ctrl.mta_in_use++;
vector = ngbe_mta_vector(hw, mc_addr);
DEBUGOUT(" bit-vector = 0x%03X\n", vector);
DEBUGOUT(" bit-vector = 0x%03X", vector);
/*
* The MTA is a register array of 128 32-bit registers. It is treated
@ -728,8 +698,6 @@ s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
u32 i;
u32 vmdq;
DEBUGFUNC("ngbe_update_mc_addr_list");
/*
* Set the new number of MC addresses that we are being requested to
* use.
@ -739,13 +707,13 @@ s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
/* Clear mta_shadow */
if (clear) {
DEBUGOUT(" Clearing MTA\n");
DEBUGOUT(" Clearing MTA");
memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
}
/* Update mta_shadow */
for (i = 0; i < mc_addr_count; i++) {
DEBUGOUT(" Adding the multicast addresses:\n");
DEBUGOUT(" Adding the multicast addresses:");
ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
}
@ -762,7 +730,7 @@ s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
wr32(hw, NGBE_PSRCTL, psrctl);
}
DEBUGOUT("ngbe update mc addr list complete\n");
DEBUGOUT("ngbe update mc addr list complete");
return 0;
}
@ -777,11 +745,9 @@ s32 ngbe_setup_fc_em(struct ngbe_hw *hw)
s32 err = 0;
u16 reg_cu = 0;
DEBUGFUNC("ngbe_setup_fc");
/* Validate the requested mode */
if (hw->fc.strict_ieee && hw->fc.requested_mode == ngbe_fc_rx_pause) {
DEBUGOUT("ngbe_fc_rx_pause not valid in strict IEEE mode\n");
DEBUGOUT("ngbe_fc_rx_pause not valid in strict IEEE mode");
err = NGBE_ERR_INVALID_LINK_SETTINGS;
goto out;
}
@ -837,7 +803,7 @@ s32 ngbe_setup_fc_em(struct ngbe_hw *hw)
reg_cu |= 0xC00; /*need to merge rtl and mvl on page 0*/
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
DEBUGOUT("Flow control param set incorrectly");
err = NGBE_ERR_CONFIG;
goto out;
}
@ -861,8 +827,6 @@ s32 ngbe_fc_enable(struct ngbe_hw *hw)
u32 pause_time;
u32 fcrtl, fcrth;
DEBUGFUNC("ngbe_fc_enable");
/* Validate the water mark configuration */
if (!hw->fc.pause_time) {
err = NGBE_ERR_INVALID_LINK_SETTINGS;
@ -873,7 +837,7 @@ s32 ngbe_fc_enable(struct ngbe_hw *hw)
if ((hw->fc.current_mode & ngbe_fc_tx_pause) && hw->fc.high_water) {
if (!hw->fc.low_water ||
hw->fc.low_water >= hw->fc.high_water) {
DEBUGOUT("Invalid water mark configuration\n");
DEBUGOUT("Invalid water mark configuration");
err = NGBE_ERR_INVALID_LINK_SETTINGS;
goto out;
}
@ -929,7 +893,7 @@ s32 ngbe_fc_enable(struct ngbe_hw *hw)
fccfg_reg |= NGBE_TXFCCFG_FC;
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
DEBUGOUT("Flow control param set incorrectly");
err = NGBE_ERR_CONFIG;
goto out;
}
@ -987,8 +951,7 @@ s32 ngbe_negotiate_fc(struct ngbe_hw *hw, u32 adv_reg, u32 lp_reg,
u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
{
if ((!(adv_reg)) || (!(lp_reg))) {
DEBUGOUT("Local or link partner's advertised flow control "
"settings are NULL. Local: %x, link partner: %x\n",
DEBUGOUT("Local or link partner's advertised flow control settings are NULL. Local: %x, link partner: %x",
adv_reg, lp_reg);
return NGBE_ERR_FC_NOT_NEGOTIATED;
}
@ -1003,22 +966,22 @@ s32 ngbe_negotiate_fc(struct ngbe_hw *hw, u32 adv_reg, u32 lp_reg,
*/
if (hw->fc.requested_mode == ngbe_fc_full) {
hw->fc.current_mode = ngbe_fc_full;
DEBUGOUT("Flow Control = FULL.\n");
DEBUGOUT("Flow Control = FULL.");
} else {
hw->fc.current_mode = ngbe_fc_rx_pause;
DEBUGOUT("Flow Control=RX PAUSE frames only\n");
DEBUGOUT("Flow Control=RX PAUSE frames only");
}
} else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
hw->fc.current_mode = ngbe_fc_tx_pause;
DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
DEBUGOUT("Flow Control = TX PAUSE frames only.");
} else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
!(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
hw->fc.current_mode = ngbe_fc_rx_pause;
DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
DEBUGOUT("Flow Control = RX PAUSE frames only.");
} else {
hw->fc.current_mode = ngbe_fc_none;
DEBUGOUT("Flow Control = NONE.\n");
DEBUGOUT("Flow Control = NONE.");
}
return 0;
}
@ -1056,8 +1019,6 @@ void ngbe_fc_autoneg(struct ngbe_hw *hw)
u32 speed;
bool link_up;
DEBUGFUNC("ngbe_fc_autoneg");
/*
* AN should have completed when the cable was plugged in.
* Look for reasons to bail out. Bail out if:
@ -1101,8 +1062,6 @@ s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)
u16 addr = 0x04;
u32 data, i;
DEBUGFUNC("ngbe_set_pcie_master");
ngbe_hic_pcie_read(hw, addr, &data, 4);
if (enable)
data |= 0x04;
@ -1126,7 +1085,7 @@ s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)
goto out;
}
DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
DEBUGOUT("PCIe transaction pending bit also did not clear.");
status = NGBE_ERR_MASTER_REQUESTS_PENDING;
out:
@ -1150,8 +1109,6 @@ s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
u32 timeout = 200;
u32 i;
DEBUGFUNC("ngbe_acquire_swfw_sync");
for (i = 0; i < timeout; i++) {
/*
* SW NVM semaphore bit is used for access to all
@ -1174,7 +1131,7 @@ s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
}
fwsm = rd32(hw, NGBE_MNGFWSYNC);
DEBUGOUT("SWFW semaphore not granted: MNG_SWFW_SYNC = 0x%x, MNG_FW_SM = 0x%x\n",
DEBUGOUT("SWFW semaphore not granted: MNG_SWFW_SYNC = 0x%x, MNG_FW_SM = 0x%x",
mngsem, fwsm);
msec_delay(5);
@ -1194,8 +1151,6 @@ void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
u32 mngsem;
u32 swmask = mask;
DEBUGFUNC("ngbe_release_swfw_sync");
ngbe_get_eeprom_semaphore(hw);
mngsem = rd32(hw, NGBE_MNGSEM);
@ -1219,9 +1174,6 @@ s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
int i;
u32 secrxreg;
DEBUGFUNC("ngbe_disable_sec_rx_path");
secrxreg = rd32(hw, NGBE_SECRXCTL);
secrxreg |= NGBE_SECRXCTL_XDSA;
wr32(hw, NGBE_SECRXCTL, secrxreg);
@ -1236,8 +1188,7 @@ s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
/* For informational purposes only */
if (i >= NGBE_MAX_SECRX_POLL)
DEBUGOUT("Rx unit being enabled before security "
"path fully disabled. Continuing with init.\n");
DEBUGOUT("Rx unit being enabled before security path fully disabled. Continuing with init.");
return 0;
}
@ -1252,8 +1203,6 @@ s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
{
u32 secrxreg;
DEBUGFUNC("ngbe_enable_sec_rx_path");
secrxreg = rd32(hw, NGBE_SECRXCTL);
secrxreg &= ~NGBE_SECRXCTL_XDSA;
wr32(hw, NGBE_SECRXCTL, secrxreg);
@ -1273,11 +1222,9 @@ s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
u32 mpsar;
u32 rar_entries = hw->mac.num_rar_entries;
DEBUGFUNC("ngbe_clear_vmdq");
/* Make sure we are using a valid rar index range */
if (rar >= rar_entries) {
DEBUGOUT("RAR index %d is out of range.\n", rar);
DEBUGOUT("RAR index %d is out of range.", rar);
return NGBE_ERR_INVALID_ARGUMENT;
}
@ -1311,11 +1258,9 @@ s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
u32 mpsar;
u32 rar_entries = hw->mac.num_rar_entries;
DEBUGFUNC("ngbe_set_vmdq");
/* Make sure we are using a valid rar index range */
if (rar >= rar_entries) {
DEBUGOUT("RAR index %d is out of range.\n", rar);
DEBUGOUT("RAR index %d is out of range.", rar);
return NGBE_ERR_INVALID_ARGUMENT;
}
@ -1336,8 +1281,7 @@ s32 ngbe_init_uta_tables(struct ngbe_hw *hw)
{
int i;
DEBUGFUNC("ngbe_init_uta_tables");
DEBUGOUT(" Clearing UTA\n");
DEBUGOUT(" Clearing UTA");
for (i = 0; i < 128; i++)
wr32(hw, NGBE_UCADDRTBL(i), 0);
@ -1392,7 +1336,7 @@ s32 ngbe_find_vlvf_slot(struct ngbe_hw *hw, u32 vlan, bool vlvf_bypass)
* slot we found during our search, else error.
*/
if (!first_empty_slot)
DEBUGOUT("No space in VLVF.\n");
DEBUGOUT("No space in VLVF.");
return first_empty_slot ? first_empty_slot : NGBE_ERR_NO_SPACE;
}
@ -1413,8 +1357,6 @@ s32 ngbe_set_vfta(struct ngbe_hw *hw, u32 vlan, u32 vind,
u32 regidx, vfta_delta, vfta;
s32 err;
DEBUGFUNC("ngbe_set_vfta");
if (vlan > 4095 || vind > 63)
return NGBE_ERR_PARAM;
@ -1482,8 +1424,6 @@ s32 ngbe_set_vlvf(struct ngbe_hw *hw, u32 vlan, u32 vind,
u32 portctl;
s32 vlvf_index;
DEBUGFUNC("ngbe_set_vlvf");
if (vlan > 4095 || vind > 63)
return NGBE_ERR_PARAM;
@ -1563,8 +1503,6 @@ s32 ngbe_clear_vfta(struct ngbe_hw *hw)
{
u32 offset;
DEBUGFUNC("ngbe_clear_vfta");
for (offset = 0; offset < hw->mac.vft_size; offset++)
wr32(hw, NGBE_VLANTBL(offset), 0);
@ -1592,8 +1530,6 @@ s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed,
u32 i, reg;
s32 status = 0;
DEBUGFUNC("ngbe_check_mac_link_em");
reg = rd32(hw, NGBE_GPIOINTSTAT);
wr32(hw, NGBE_GPIOEOI, reg);
@ -1617,7 +1553,6 @@ s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,
{
s32 status = 0;
u16 value = 0;
DEBUGFUNC("\n");
hw->mac.autoneg = *autoneg;
@ -1642,8 +1577,6 @@ s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw,
{
s32 status;
DEBUGFUNC("\n");
/* Setup the PHY according to input speed */
status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete);
@ -1723,8 +1656,6 @@ s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
{
struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
DEBUGFUNC("ngbe_init_thermal_sensor_thresh");
memset(data, 0, sizeof(struct ngbe_thermal_sensor_data));
if (hw->bus.lan_id != 0)
@ -1748,8 +1679,6 @@ s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)
s32 status = 0;
u32 ts_state;
DEBUGFUNC("ngbe_mac_check_overtemp");
/* Check that the LASI temp alarm status was triggered */
ts_state = rd32(hw, NGBE_TSALM);
@ -1804,8 +1733,6 @@ s32 ngbe_set_mac_type(struct ngbe_hw *hw)
{
s32 err = 0;
DEBUGFUNC("ngbe_set_mac_type");
if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
return NGBE_ERR_DEVICE_NOT_SUPPORTED;
@ -1846,7 +1773,7 @@ s32 ngbe_set_mac_type(struct ngbe_hw *hw)
break;
}
DEBUGOUT("found mac: %d media: %d, returns: %d\n",
DEBUGOUT("found mac: %d media: %d, returns: %d",
hw->mac.type, hw->phy.media_type, err);
return err;
}
@ -1860,15 +1787,12 @@ s32 ngbe_set_mac_type(struct ngbe_hw *hw)
**/
s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
{
DEBUGFUNC("ngbe_enable_rx_dma");
/*
* Workaround silicon errata when enabling the Rx datapath.
* If traffic is incoming before we enable the Rx unit, it could hang
* the Rx DMA unit. Therefore, make sure the security engine is
* completely disabled prior to enabling the Rx unit.
*/
hw->mac.disable_sec_rx_path(hw);
if (regval & NGBE_PBRXCTL_ENA)
@ -1960,8 +1884,6 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
struct ngbe_rom_info *rom = &hw->rom;
struct ngbe_mbx_info *mbx = &hw->mbx;
DEBUGFUNC("ngbe_init_ops_pf");
/* BUS */
bus->set_lan_id = ngbe_set_lan_id_multi_port;
@ -2064,8 +1986,6 @@ s32 ngbe_init_shared_code(struct ngbe_hw *hw)
{
s32 status = 0;
DEBUGFUNC("ngbe_init_shared_code");
/*
* Set the mac type
*/

22
drivers/net/ngbe/base/ngbe_mbx.c
View File

@ -21,8 +21,6 @@ s32 ngbe_read_mbx(struct ngbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
struct ngbe_mbx_info *mbx = &hw->mbx;
s32 ret_val = NGBE_ERR_MBX;
DEBUGFUNC("ngbe_read_mbx");
/* limit read to size of mailbox */
if (size > mbx->size)
size = mbx->size;
@ -47,8 +45,6 @@ s32 ngbe_write_mbx(struct ngbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
struct ngbe_mbx_info *mbx = &hw->mbx;
s32 ret_val = 0;
DEBUGFUNC("ngbe_write_mbx");
if (size > mbx->size) {
ret_val = NGBE_ERR_MBX;
DEBUGOUT("Invalid mailbox message size %d", size);
@ -71,8 +67,6 @@ s32 ngbe_check_for_msg(struct ngbe_hw *hw, u16 mbx_id)
struct ngbe_mbx_info *mbx = &hw->mbx;
s32 ret_val = NGBE_ERR_MBX;
DEBUGFUNC("ngbe_check_for_msg");
if (mbx->check_for_msg)
ret_val = mbx->check_for_msg(hw, mbx_id);
@ -91,8 +85,6 @@ s32 ngbe_check_for_ack(struct ngbe_hw *hw, u16 mbx_id)
struct ngbe_mbx_info *mbx = &hw->mbx;
s32 ret_val = NGBE_ERR_MBX;
DEBUGFUNC("ngbe_check_for_ack");
if (mbx->check_for_ack)
ret_val = mbx->check_for_ack(hw, mbx_id);
@ -111,8 +103,6 @@ s32 ngbe_check_for_rst(struct ngbe_hw *hw, u16 mbx_id)
struct ngbe_mbx_info *mbx = &hw->mbx;
s32 ret_val = NGBE_ERR_MBX;
DEBUGFUNC("ngbe_check_for_rst");
if (mbx->check_for_rst)
ret_val = mbx->check_for_rst(hw, mbx_id);
@ -144,8 +134,6 @@ s32 ngbe_check_for_msg_pf(struct ngbe_hw *hw, u16 vf_number)
s32 ret_val = NGBE_ERR_MBX;
u32 vf_bit = vf_number;
DEBUGFUNC("ngbe_check_for_msg_pf");
if (!ngbe_check_for_bit_pf(hw, NGBE_MBVFICR_VFREQ_VF1 << vf_bit)) {
ret_val = 0;
hw->mbx.stats.reqs++;
@ -166,8 +154,6 @@ s32 ngbe_check_for_ack_pf(struct ngbe_hw *hw, u16 vf_number)
s32 ret_val = NGBE_ERR_MBX;
u32 vf_bit = vf_number;
DEBUGFUNC("ngbe_check_for_ack_pf");
if (!ngbe_check_for_bit_pf(hw, NGBE_MBVFICR_VFACK_VF1 << vf_bit)) {
ret_val = 0;
hw->mbx.stats.acks++;
@ -188,8 +174,6 @@ s32 ngbe_check_for_rst_pf(struct ngbe_hw *hw, u16 vf_number)
u32 vflre = 0;
s32 ret_val = NGBE_ERR_MBX;
DEBUGFUNC("ngbe_check_for_rst_pf");
vflre = rd32(hw, NGBE_FLRVFE);
if (vflre & (1 << vf_number)) {
ret_val = 0;
@ -212,8 +196,6 @@ STATIC s32 ngbe_obtain_mbx_lock_pf(struct ngbe_hw *hw, u16 vf_number)
s32 ret_val = NGBE_ERR_MBX;
u32 p2v_mailbox;
DEBUGFUNC("ngbe_obtain_mbx_lock_pf");
/* Take ownership of the buffer */
wr32(hw, NGBE_MBCTL(vf_number), NGBE_MBCTL_PFU);
@ -242,8 +224,6 @@ s32 ngbe_write_mbx_pf(struct ngbe_hw *hw, u32 *msg, u16 size, u16 vf_number)
s32 ret_val;
u16 i;
DEBUGFUNC("ngbe_write_mbx_pf");
/* lock the mailbox to prevent pf/vf race condition */
ret_val = ngbe_obtain_mbx_lock_pf(hw, vf_number);
if (ret_val)
@ -283,8 +263,6 @@ s32 ngbe_read_mbx_pf(struct ngbe_hw *hw, u32 *msg, u16 size, u16 vf_number)
s32 ret_val;
u16 i;
DEBUGFUNC("ngbe_read_mbx_pf");
/* lock the mailbox to prevent pf/vf race condition */
ret_val = ngbe_obtain_mbx_lock_pf(hw, vf_number);
if (ret_val)

16
drivers/net/ngbe/base/ngbe_mng.c
View File

@ -26,10 +26,8 @@ ngbe_hic_unlocked(struct ngbe_hw *hw, u32 *buffer, u32 length, u32 timeout)
u32 value, loop;
u16 i, dword_len;
DEBUGFUNC("ngbe_hic_unlocked");
if (!length || length > NGBE_PMMBX_BSIZE) {
DEBUGOUT("Buffer length failure buffersize=%d.\n", length);
DEBUGOUT("Buffer length failure buffersize=%d.", length);
return NGBE_ERR_HOST_INTERFACE_COMMAND;
}
@ -59,7 +57,7 @@ ngbe_hic_unlocked(struct ngbe_hw *hw, u32 *buffer, u32 length, u32 timeout)
NGBE_MNGMBXCTL_FWRDY, NGBE_MNGMBXCTL_FWRDY,
&value, timeout, 1000);
if (!loop || !(value & NGBE_MNGMBXCTL_FWACK)) {
DEBUGOUT("Command has failed with no status valid.\n");
DEBUGOUT("Command has failed with no status valid.");
return NGBE_ERR_HOST_INTERFACE_COMMAND;
}
@ -95,10 +93,8 @@ ngbe_host_interface_command(struct ngbe_hw *hw, u32 *buffer,
u32 bi;
u32 dword_len;
DEBUGFUNC("ngbe_host_interface_command");
if (length == 0 || length > NGBE_PMMBX_BSIZE) {
DEBUGOUT("Buffer length failure buffersize=%d.\n", length);
DEBUGOUT("Buffer length failure buffersize=%d.", length);
return NGBE_ERR_HOST_INTERFACE_COMMAND;
}
@ -140,7 +136,7 @@ ngbe_host_interface_command(struct ngbe_hw *hw, u32 *buffer,
goto rel_out;
if (length < buf_len + hdr_size) {
DEBUGOUT("Buffer not large enough for reply message.\n");
DEBUGOUT("Buffer not large enough for reply message.");
err = NGBE_ERR_HOST_INTERFACE_COMMAND;
goto rel_out;
}
@ -306,8 +302,6 @@ s32 ngbe_hic_check_cap(struct ngbe_hw *hw)
s32 err;
int i;
DEBUGFUNC("\n");
command.hdr.req.cmd = FW_EEPROM_CHECK_STATUS;
command.hdr.req.buf_lenh = 0;
command.hdr.req.buf_lenl = 0;
@ -345,8 +339,6 @@ s32 ngbe_phy_led_oem_chk(struct ngbe_hw *hw, u32 *data)
s32 err;
int i;
DEBUGFUNC("\n");
command.hdr.req.cmd = FW_PHY_LED_CONF;
command.hdr.req.buf_lenh = 0;
command.hdr.req.buf_lenl = 0;

30
drivers/net/ngbe/base/ngbe_phy.c
View File

@ -46,7 +46,7 @@ s32 ngbe_mdi_map_register(mdi_reg_t *reg, mdi_reg_22_t *reg22)
static bool ngbe_probe_phy(struct ngbe_hw *hw, u16 phy_addr)
{
if (!ngbe_validate_phy_addr(hw, phy_addr)) {
DEBUGOUT("Unable to validate PHY address 0x%04X\n",
DEBUGOUT("Unable to validate PHY address 0x%04X",
phy_addr);
return false;
}
@ -71,8 +71,6 @@ s32 ngbe_identify_phy(struct ngbe_hw *hw)
s32 err = NGBE_ERR_PHY_ADDR_INVALID;
u16 phy_addr;
DEBUGFUNC("ngbe_identify_phy");
if (hw->phy.type != ngbe_phy_unknown)
return 0;
@ -102,11 +100,9 @@ s32 ngbe_check_reset_blocked(struct ngbe_hw *hw)
{
u32 mmngc;
DEBUGFUNC("ngbe_check_reset_blocked");
mmngc = rd32(hw, NGBE_STAT);
if (mmngc & NGBE_STAT_MNGVETO) {
DEBUGOUT("MNG_VETO bit detected.\n");
DEBUGOUT("MNG_VETO bit detected.");
return true;
}
@ -124,8 +120,6 @@ bool ngbe_validate_phy_addr(struct ngbe_hw *hw, u32 phy_addr)
u16 phy_id = 0;
bool valid = false;
DEBUGFUNC("ngbe_validate_phy_addr");
if (hw->sub_device_id == NGBE_SUB_DEV_ID_EM_YT8521S_SFP)
return true;
@ -136,7 +130,7 @@ bool ngbe_validate_phy_addr(struct ngbe_hw *hw, u32 phy_addr)
if (phy_id != 0xFFFF && phy_id != 0x0)
valid = true;
DEBUGOUT("PHY ID HIGH is 0x%04X\n", phy_id);
DEBUGOUT("PHY ID HIGH is 0x%04X", phy_id);
return valid;
}
@ -152,8 +146,6 @@ s32 ngbe_get_phy_id(struct ngbe_hw *hw)
u16 phy_id_high = 0;
u16 phy_id_low = 0;
DEBUGFUNC("ngbe_get_phy_id");
err = hw->phy.read_reg(hw, NGBE_MD_PHY_ID_HIGH,
NGBE_MD_DEV_PMA_PMD,
&phy_id_high);
@ -165,7 +157,7 @@ s32 ngbe_get_phy_id(struct ngbe_hw *hw)
hw->phy.id |= (u32)(phy_id_low & NGBE_PHY_REVISION_MASK);
hw->phy.revision = (u32)(phy_id_low & ~NGBE_PHY_REVISION_MASK);
DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X",
phy_id_high, phy_id_low);
return err;
@ -179,8 +171,6 @@ s32 ngbe_get_phy_type_from_id(struct ngbe_hw *hw)
{
s32 status = 0;
DEBUGFUNC("ngbe_get_phy_type_from_id");
switch (hw->phy.id) {
case NGBE_PHYID_RTL:
hw->phy.type = ngbe_phy_rtl;
@ -216,8 +206,6 @@ s32 ngbe_reset_phy(struct ngbe_hw *hw)
{
s32 err = 0;
DEBUGFUNC("ngbe_reset_phy");
if (hw->phy.type == ngbe_phy_unknown)
err = ngbe_identify_phy(hw);
@ -282,7 +270,7 @@ s32 ngbe_read_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
*/
if (!po32m(hw, NGBE_MDIOSCD, NGBE_MDIOSCD_BUSY,
0, NULL, 100, 100)) {
DEBUGOUT("PHY address command did not complete\n");
DEBUGOUT("PHY address command did not complete");
return NGBE_ERR_PHY;
}
@ -306,8 +294,6 @@ s32 ngbe_read_phy_reg(struct ngbe_hw *hw, u32 reg_addr,
s32 err;
u32 gssr = hw->phy.phy_semaphore_mask;
DEBUGFUNC("ngbe_read_phy_reg");
if (hw->mac.acquire_swfw_sync(hw, gssr))
return NGBE_ERR_SWFW_SYNC;
@ -347,7 +333,7 @@ s32 ngbe_write_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr,
/* wait for completion */
if (!po32m(hw, NGBE_MDIOSCD, NGBE_MDIOSCD_BUSY,
0, NULL, 100, 100)) {
TLOG_DEBUG("PHY write cmd didn't complete\n");
DEBUGOUT("PHY write cmd didn't complete");
return NGBE_ERR_PHY;
}
@ -368,8 +354,6 @@ s32 ngbe_write_phy_reg(struct ngbe_hw *hw, u32 reg_addr,
s32 err;
u32 gssr = hw->phy.phy_semaphore_mask;
DEBUGFUNC("ngbe_write_phy_reg");
if (hw->mac.acquire_swfw_sync(hw, gssr))
err = NGBE_ERR_SWFW_SYNC;
@ -395,8 +379,6 @@ s32 ngbe_init_phy(struct ngbe_hw *hw)
struct ngbe_phy_info *phy = &hw->phy;
s32 err = 0;
DEBUGFUNC("ngbe_init_phy");
hw->phy.addr = 0;
switch (hw->sub_device_id) {

17
drivers/net/ngbe/base/ngbe_phy_mvl.c
View File

@ -66,7 +66,7 @@ s32 ngbe_check_phy_mode_mvl(struct ngbe_hw *hw)
hw->phy.media_type = ngbe_media_type_fiber;
hw->mac.link_type = ngbe_link_fiber;
} else {
DEBUGOUT("marvell 88E1512 mode %x is not supported.\n", value);
DEBUGOUT("marvell 88E1512 mode %x is not supported.", value);
return NGBE_ERR_DEVICE_NOT_SUPPORTED;
}
@ -79,8 +79,6 @@ s32 ngbe_init_phy_mvl(struct ngbe_hw *hw)
u16 value = 0;
int i;
DEBUGFUNC("ngbe_init_phy_mvl");
/* enable interrupts, only link status change and an done is allowed */
ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 2);
ngbe_read_phy_reg_mdi(hw, MVL_RGM_CTL2, 0, &value);
@ -98,7 +96,7 @@ s32 ngbe_init_phy_mvl(struct ngbe_hw *hw)
}
if (i == 15) {
DEBUGOUT("phy reset exceeds maximum waiting period.\n");
DEBUGOUT("phy reset exceeds maximum waiting period.");
return NGBE_ERR_TIMEOUT;
}
@ -137,7 +135,6 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
u16 value_r9 = 0;
u16 value;
DEBUGFUNC("ngbe_setup_phy_link_mvl");
UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
if (hw->led_conf == 0xFFFF) {
@ -170,7 +167,7 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
default:
value = MVL_CTRL_SPEED_SELECT0 |
MVL_CTRL_SPEED_SELECT1;
DEBUGOUT("unknown speed = 0x%x.\n", speed);
DEBUGOUT("unknown speed = 0x%x.", speed);
break;
}
/* duplex full */
@ -235,8 +232,6 @@ s32 ngbe_reset_phy_mvl(struct ngbe_hw *hw)
u16 ctrl = 0;
s32 status = 0;
DEBUGFUNC("ngbe_reset_phy_mvl");
if (hw->phy.type != ngbe_phy_mvl && hw->phy.type != ngbe_phy_mvl_sfi)
return NGBE_ERR_PHY_TYPE;
@ -261,7 +256,7 @@ s32 ngbe_reset_phy_mvl(struct ngbe_hw *hw)
}
if (i == MVL_PHY_RST_WAIT_PERIOD) {
DEBUGOUT("PHY reset polling failed to complete.\n");
DEBUGOUT("PHY reset polling failed to complete.");
return NGBE_ERR_RESET_FAILED;
}
@ -309,8 +304,6 @@ s32 ngbe_set_phy_pause_adv_mvl(struct ngbe_hw *hw, u16 pause_bit)
u16 value;
s32 status = 0;
DEBUGFUNC("ngbe_set_phy_pause_adv_mvl");
if (hw->phy.type == ngbe_phy_mvl) {
status = hw->phy.read_reg(hw, MVL_ANA, 0, &value);
value &= ~(MVL_CANA_ASM_PAUSE | MVL_CANA_PAUSE);
@ -334,8 +327,6 @@ s32 ngbe_check_phy_link_mvl(struct ngbe_hw *hw,
u16 phy_data = 0;
u16 insr = 0;
DEBUGFUNC("ngbe_check_phy_link_mvl");
/* Initialize speed and link to default case */
*link_up = false;
*speed = NGBE_LINK_SPEED_UNKNOWN;

18
drivers/net/ngbe/base/ngbe_phy_rtl.c
View File

@ -79,14 +79,14 @@ s32 ngbe_init_phy_rtl(struct ngbe_hw *hw)
msec_delay(10);
}
if (i == 15) {
DEBUGOUT("GPhy reset exceeds maximum times.\n");
DEBUGOUT("GPhy reset exceeds maximum times.");
return NGBE_ERR_PHY_TIMEOUT;
}
hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EFUSE);
hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value);
if (!(value & RTL_SCR_EFUSE)) {
DEBUGOUT("Write EFUSE failed.\n");
DEBUGOUT("Write EFUSE failed.");
return NGBE_ERR_PHY_TIMEOUT;
}
@ -97,13 +97,13 @@ s32 ngbe_init_phy_rtl(struct ngbe_hw *hw)
msec_delay(1);
}
if (i == 1000)
DEBUGOUT("PHY wait mdio 1 access timeout.\n");
DEBUGOUT("PHY wait mdio 1 access timeout.");
hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EXTINI);
hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value);
if (!(value & RTL_SCR_EXTINI)) {
DEBUGOUT("Write EXIINI failed.\n");
DEBUGOUT("Write EXIINI failed.");
return NGBE_ERR_PHY_TIMEOUT;
}
@ -114,7 +114,7 @@ s32 ngbe_init_phy_rtl(struct ngbe_hw *hw)
msec_delay(1);
}
if (i == 1000)
DEBUGOUT("PHY wait mdio 2 access timeout.\n");
DEBUGOUT("PHY wait mdio 2 access timeout.");
for (i = 0; i < 1000; i++) {
hw->phy.read_reg(hw, RTL_GSR, 0xa42, &value);
@ -140,8 +140,6 @@ s32 ngbe_setup_phy_link_rtl(struct ngbe_hw *hw,
u16 autoneg_reg = NGBE_MII_AUTONEG_REG;
u16 value = 0;
DEBUGFUNC("ngbe_setup_phy_link_rtl");
UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
hw->phy.read_reg(hw, RTL_INSR, 0xa43, &autoneg_reg);
@ -161,7 +159,7 @@ s32 ngbe_setup_phy_link_rtl(struct ngbe_hw *hw,
break;
default:
value = RTL_BMCR_SPEED_SELECT1 | RTL_BMCR_SPEED_SELECT0;
DEBUGOUT("unknown speed = 0x%x.\n", speed);
DEBUGOUT("unknown speed = 0x%x.", speed);
break;
}
/* duplex full */
@ -253,8 +251,6 @@ s32 ngbe_reset_phy_rtl(struct ngbe_hw *hw)
u16 value = 0;
s32 status = 0;
DEBUGFUNC("ngbe_reset_phy_rtl");
value |= RTL_BMCR_RESET;
status = hw->phy.write_reg(hw, RTL_BMCR, RTL_DEV_ZERO, value);
@ -313,8 +309,6 @@ s32 ngbe_check_phy_link_rtl(struct ngbe_hw *hw, u32 *speed, bool *link_up)
u16 phy_data = 0;
u16 insr = 0;
DEBUGFUNC("ngbe_check_phy_link_rtl");
hw->phy.read_reg(hw, RTL_INSR, 0xa43, &insr);
/* Initialize speed and link to default case */

18
drivers/net/ngbe/base/ngbe_phy_yt.c
View File

@ -102,8 +102,6 @@ s32 ngbe_init_phy_yt(struct ngbe_hw *hw)
{
u16 value = 0;
DEBUGFUNC("ngbe_init_phy_yt");
/* close sds area register */
ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
/* enable interrupts */
@ -130,7 +128,6 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
u16 value_r9 = 0;
u16 value;
DEBUGFUNC("ngbe_setup_phy_link_yt");
UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
hw->phy.autoneg_advertised = 0;
@ -153,7 +150,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
default:
value = YT_BCR_SPEED_SELECT0 |
YT_BCR_SPEED_SELECT1;
DEBUGOUT("unknown speed = 0x%x.\n",
DEBUGOUT("unknown speed = 0x%x.",
speed);
break;
}
@ -324,8 +321,6 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw)
u16 ctrl = 0;
s32 status = 0;
DEBUGFUNC("ngbe_reset_phy_yt");
if (hw->phy.type != ngbe_phy_yt8521s &&
hw->phy.type != ngbe_phy_yt8521s_sfi)
return NGBE_ERR_PHY_TYPE;
@ -361,7 +356,7 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw)
}
if (i == YT_PHY_RST_WAIT_PERIOD) {
DEBUGOUT("PHY reset polling failed to complete.\n");
DEBUGOUT("PHY reset polling failed to complete.");
return NGBE_ERR_RESET_FAILED;
}
@ -373,8 +368,6 @@ s32 ngbe_get_phy_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit)
u16 value;
s32 status = 0;
DEBUGFUNC("ngbe_get_phy_advertised_pause_yt");
status = hw->phy.read_reg(hw, YT_ANA, 0, &value);
value &= YT_FANA_PAUSE_MASK;
*pause_bit = (u8)(value >> 7);
@ -387,8 +380,6 @@ s32 ngbe_get_phy_lp_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit)
u16 value;
s32 status = 0;
DEBUGFUNC("ngbe_get_phy_lp_advertised_pause_yt");
status = hw->phy.read_reg(hw, YT_LPAR, 0, &value);
value &= YT_FLPAR_PAUSE_MASK;
*pause_bit = (u8)(value >> 7);
@ -401,9 +392,6 @@ s32 ngbe_set_phy_pause_adv_yt(struct ngbe_hw *hw, u16 pause_bit)
u16 value;
s32 status = 0;
DEBUGFUNC("ngbe_set_phy_pause_adv_yt");
status = hw->phy.read_reg(hw, YT_ANA, 0, &value);
value &= ~YT_FANA_PAUSE_MASK;
value |= pause_bit;
@ -421,8 +409,6 @@ s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw,
u16 phy_data = 0;
u16 insr = 0;
DEBUGFUNC("ngbe_check_phy_link_yt");
/* Initialize speed and link to default case */
*link_up = false;
*speed = NGBE_LINK_SPEED_UNKNOWN;

7
drivers/net/ngbe/ngbe_logs.h
View File

@ -37,10 +37,7 @@ extern int ngbe_logtype_tx;
#define PMD_TX_LOG(level, fmt, args...) do { } while (0)
#endif
#define TLOG_DEBUG(fmt, args...) PMD_DRV_LOG(DEBUG, fmt, ##args)
#define DEBUGOUT(fmt, args...) TLOG_DEBUG(fmt, ##args)
#define PMD_INIT_FUNC_TRACE() TLOG_DEBUG(" >>")
#define DEBUGFUNC(fmt) TLOG_DEBUG(fmt)
#define DEBUGOUT(fmt, args...) PMD_DRV_LOG(DEBUG, fmt, ##args)
#define PMD_INIT_FUNC_TRACE() PMD_DRV_LOG(DEBUG, ">>")
#endif /* _NGBE_LOGS_H_ */