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net/mlx5: support Mellanox OFED 3.4

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Some macros are renamed by Mellanox OFED 3.4.

Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
This commit is contained in:
Nélio Laranjeiro 2016-09-21 15:48:12 +02:00 committed by Bruce Richardson
parent 0c79d5aa1a
commit c904ae25fe
3 changed files with 13 additions and 2 deletions
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5
drivers/net/mlx5/Makefile
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@ -116,6 +116,11 @@ mlx5_autoconf.h.new: $(RTE_SDK)/scripts/auto-config-h.sh
infiniband/mlx5_hw.h \ infiniband/mlx5_hw.h \
enum MLX5_ETH_VLAN_INLINE_HEADER_SIZE \ enum MLX5_ETH_VLAN_INLINE_HEADER_SIZE \
$(AUTOCONF_OUTPUT) $(AUTOCONF_OUTPUT)
$Q sh -- '$<' '$@' \
HAVE_VERBS_MLX5_OPCODE_TSO \
infiniband/mlx5_hw.h \
enum MLX5_OPCODE_TSO \
$(AUTOCONF_OUTPUT)
# Create mlx5_autoconf.h or update it in case it differs from the new one. # Create mlx5_autoconf.h or update it in case it differs from the new one.

6
drivers/net/mlx5/mlx5_prm.h
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@ -44,6 +44,8 @@
#pragma GCC diagnostic error "-Wpedantic" #pragma GCC diagnostic error "-Wpedantic"
#endif #endif
#include "mlx5_autoconf.h"
/* Get CQE owner bit. */ /* Get CQE owner bit. */
#define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK) #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
@ -78,6 +80,10 @@
/* Room for inline data in multi-packet WQE. */ /* Room for inline data in multi-packet WQE. */
#define MLX5_MWQE64_INL_DATA 28 #define MLX5_MWQE64_INL_DATA 28
#ifndef HAVE_VERBS_MLX5_OPCODE_TSO
#define MLX5_OPCODE_TSO MLX5_OPCODE_LSO_MPW /* Compat with OFED 3.3. */
#endif
/* Subset of struct mlx5_wqe_eth_seg. */ /* Subset of struct mlx5_wqe_eth_seg. */
struct mlx5_wqe_eth_seg_small { struct mlx5_wqe_eth_seg_small {
uint32_t rsvd0; uint32_t rsvd0;

4
drivers/net/mlx5/mlx5_rxtx.c
View File

@ -628,7 +628,7 @@ mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
mpw->wqe->eseg.rsvd1 = 0; mpw->wqe->eseg.rsvd1 = 0;
mpw->wqe->eseg.rsvd2 = 0; mpw->wqe->eseg.rsvd2 = 0;
mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) | mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
(txq->wqe_ci << 8) | MLX5_OPCODE_LSO_MPW); (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
mpw->wqe->ctrl[2] = 0; mpw->wqe->ctrl[2] = 0;
mpw->wqe->ctrl[3] = 0; mpw->wqe->ctrl[3] = 0;
mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *) mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
@ -830,7 +830,7 @@ mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr; mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;
mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) | mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
(txq->wqe_ci << 8) | (txq->wqe_ci << 8) |
MLX5_OPCODE_LSO_MPW); MLX5_OPCODE_TSO);
mpw->wqe->ctrl[2] = 0; mpw->wqe->ctrl[2] = 0;
mpw->wqe->ctrl[3] = 0; mpw->wqe->ctrl[3] = 0;
mpw->wqe->eseg.mss = htons(length); mpw->wqe->eseg.mss = htons(length);