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crypto/mvsam: update queue mapping comments

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Till now comments explain queue mapping per
one and two crypto devices.
Now added comments for queue mapping for three
crypto devices supported in CN9132.

Signed-off-by: Michael Shamis <michaelsh@marvell.com>
Reviewed-by: Liron Himi <lironh@marvell.com>
This commit is contained in:
Michael Shamis 2021-07-01 10:00:05 +03:00 committed by Akhil Goyal
parent 03e73e8572
commit c9e9ca7de6
1 changed files with 15 additions and 3 deletions
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18
drivers/crypto/mvsam/rte_mrvl_pmd_ops.c
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@ -662,6 +662,11 @@ mrvl_crypto_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
}
/*
* In case just one engine is enabled mapping will look as
* follows:
* qp: 0 1 2 3
* cio-x:y: cio-0:0, cio-0:1, cio-0:2, cio-0:3
*
* In case two crypto engines are enabled qps will
* be evenly spread among them. Even and odd qps will
* be handled by cio-0 and cio-1 respectively. qp-cio mapping
@ -673,10 +678,17 @@ mrvl_crypto_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
* qp: 4 5 6 7
* cio-x:y: cio-0:2, cio-1:2, cio-0:3, cio-1:3
*
* In case just one engine is enabled mapping will look as
* follows:
* In case of three crypto engines are enabled qps will
* be mapped as following:
*
* qp: 0 1 2 3
* cio-x:y: cio-0:0, cio-0:1, cio-0:2, cio-0:3
* cio-x:y: cio-0:0, cio-1:0, cio-2:0, cio-0:1
*
* qp: 4 5 6 7
* cio-x:y: cio-1:1, cio-2:1, cio-0:2, cio-1:2
*
* qp: 8 9 10 11
* cio-x:y: cio-2:2, cio-0:3, cio-1:3, cio-2:3
*/
n = snprintf(match, sizeof(match), "cio-%u:%u",
qp_id % num, qp_id / num);