net/ice/base: implement Vernier calibration for E822
Move the implementation of Vernier calibration from Linux core ice_ptp.c into the shared ice_ptp_hw.c file. This implementation was recently refactored in Linux, so the move should be verbatim with the latest Linux code that we had implemented. This includes a new constant table with pre-determined values based on link speed, new functions to aide in reading the multi-register values from the PHY, functions to program the PAR/PCS conversion ratios, and the UIX conversion ratios, functions to program the total Tx and Rx offset after vernier calibration in the hardware completes, and finally a function to start and stop the PHY timestamping block. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Junfeng Guo <junfeng.guo@intel.com>
This commit is contained in:
Qi Zhang
parent
886b8115fc
commit
ca3feb9036
@ -157,4 +157,220 @@ const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
|
||||
},
|
||||
};
|
||||
|
||||
/* struct ice_vernier_info_e822
|
||||
*
|
||||
* E822 hardware calibrates the delay of the timestamp indication from the
|
||||
* actual packet transmission or reception during the initialization of the
|
||||
* PHY. To do this, the hardware mechanism uses some conversions between the
|
||||
* various clocks within the PHY block. This table defines constants used to
|
||||
* calculate the correct conversion ratios in the PHY registers.
|
||||
*
|
||||
* Many of the values relate to the PAR/PCS clock conversion registers. For
|
||||
* these registers, a value of 0 means that the associated register is not
|
||||
* used by this link speed, and that the register should be cleared by writing
|
||||
* 0. Other values specify the clock frequency in Hz.
|
||||
*/
|
||||
const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = {
|
||||
/* ICE_PTP_LNK_SPD_1G */
|
||||
{
|
||||
/* tx_par_clk */
|
||||
31250000, /* 31.25 MHz */
|
||||
/* rx_par_clk */
|
||||
31250000, /* 31.25 MHz */
|
||||
/* tx_pcs_clk */
|
||||
125000000, /* 125 MHz */
|
||||
/* rx_pcs_clk */
|
||||
125000000, /* 125 MHz */
|
||||
/* tx_desk_rsgb_par */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_par */
|
||||
0, /* unused */
|
||||
/* tx_desk_rsgb_pcs */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_pcs */
|
||||
0, /* unused */
|
||||
/* tx_fixed_delay */
|
||||
25140,
|
||||
/* pmd_adj_divisor */
|
||||
10000000,
|
||||
/* rx_fixed_delay */
|
||||
17372,
|
||||
},
|
||||
/* ICE_PTP_LNK_SPD_10G */
|
||||
{
|
||||
/* tx_par_clk */
|
||||
257812500, /* 257.8125 MHz */
|
||||
/* rx_par_clk */
|
||||
257812500, /* 257.8125 MHz */
|
||||
/* tx_pcs_clk */
|
||||
156250000, /* 156.25 MHz */
|
||||
/* rx_pcs_clk */
|
||||
156250000, /* 156.25 MHz */
|
||||
/* tx_desk_rsgb_par */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_par */
|
||||
0, /* unused */
|
||||
/* tx_desk_rsgb_pcs */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_pcs */
|
||||
0, /* unused */
|
||||
/* tx_fixed_delay */
|
||||
6938,
|
||||
/* pmd_adj_divisor */
|
||||
82500000,
|
||||
/* rx_fixed_delay */
|
||||
6212,
|
||||
},
|
||||
/* ICE_PTP_LNK_SPD_25G */
|
||||
{
|
||||
/* tx_par_clk */
|
||||
644531250, /* 644.53125 MHZ */
|
||||
/* rx_par_clk */
|
||||
644531250, /* 644.53125 MHz */
|
||||
/* tx_pcs_clk */
|
||||
390625000, /* 390.625 MHz */
|
||||
/* rx_pcs_clk */
|
||||
390625000, /* 390.625 MHz */
|
||||
/* tx_desk_rsgb_par */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_par */
|
||||
0, /* unused */
|
||||
/* tx_desk_rsgb_pcs */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_pcs */
|
||||
0, /* unused */
|
||||
/* tx_fixed_delay */
|
||||
2778,
|
||||
/* pmd_adj_divisor */
|
||||
206250000,
|
||||
/* rx_fixed_delay */
|
||||
2491,
|
||||
},
|
||||
/* ICE_PTP_LNK_SPD_25G_RS */
|
||||
{
|
||||
/* tx_par_clk */
|
||||
0, /* unused */
|
||||
/* rx_par_clk */
|
||||
0, /* unused */
|
||||
/* tx_pcs_clk */
|
||||
0, /* unused */
|
||||
/* rx_pcs_clk */
|
||||
0, /* unused */
|
||||
/* tx_desk_rsgb_par */
|
||||
161132812, /* 162.1328125 MHz Reed Solomon gearbox */
|
||||
/* rx_desk_rsgb_par */
|
||||
161132812, /* 162.1328125 MHz Reed Solomon gearbox */
|
||||
/* tx_desk_rsgb_pcs */
|
||||
97656250, /* 97.62625 MHz Reed Solomon gearbox */
|
||||
/* rx_desk_rsgb_pcs */
|
||||
97656250, /* 97.62625 MHz Reed Solomon gearbox */
|
||||
/* tx_fixed_delay */
|
||||
3928,
|
||||
/* pmd_adj_divisor */
|
||||
206250000,
|
||||
/* rx_fixed_delay */
|
||||
29535,
|
||||
},
|
||||
/* ICE_PTP_LNK_SPD_40G */
|
||||
{
|
||||
/* tx_par_clk */
|
||||
257812500,
|
||||
/* rx_par_clk */
|
||||
257812500,
|
||||
/* tx_pcs_clk */
|
||||
156250000, /* 156.25 MHz */
|
||||
/* rx_pcs_clk */
|
||||
156250000, /* 156.25 MHz */
|
||||
/* tx_desk_rsgb_par */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_par */
|
||||
156250000, /* 156.25 MHz deskew clock */
|
||||
/* tx_desk_rsgb_pcs */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_pcs */
|
||||
156250000, /* 156.25 MHz deskew clock */
|
||||
/* tx_fixed_delay */
|
||||
5666,
|
||||
/* pmd_adj_divisor */
|
||||
82500000,
|
||||
/* rx_fixed_delay */
|
||||
4244,
|
||||
},
|
||||
/* ICE_PTP_LNK_SPD_50G */
|
||||
{
|
||||
/* tx_par_clk */
|
||||
644531250, /* 644.53125 MHZ */
|
||||
/* rx_par_clk */
|
||||
644531250, /* 644.53125 MHZ */
|
||||
/* tx_pcs_clk */
|
||||
390625000, /* 390.625 MHz */
|
||||
/* rx_pcs_clk */
|
||||
390625000, /* 390.625 MHz */
|
||||
/* tx_desk_rsgb_par */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_par */
|
||||
195312500, /* 193.3125 MHz deskew clock */
|
||||
/* tx_desk_rsgb_pcs */
|
||||
0, /* unused */
|
||||
/* rx_desk_rsgb_pcs */
|
||||
195312500, /* 193.3125 MHz deskew clock */
|
||||
/* tx_fixed_delay */
|
||||
2778,
|
||||
/* pmd_adj_divisor */
|
||||
206250000,
|
||||
/* rx_fixed_delay */
|
||||
2868,
|
||||
},
|
||||
/* ICE_PTP_LNK_SPD_50G_RS */
|
||||
{
|
||||
/* tx_par_clk */
|
||||
0, /* unused */
|
||||
/* rx_par_clk */
|
||||
644531250, /* 644.53125 MHz */
|
||||
/* tx_pcs_clk */
|
||||
0, /* unused */
|
||||
/* rx_pcs_clk */
|
||||
644531250, /* 644.53125 MHz */
|
||||
/* tx_desk_rsgb_par */
|
||||
322265625, /* 322.265625 MHz Reed Solomon gearbox */
|
||||
/* rx_desk_rsgb_par */
|
||||
322265625, /* 322.265625 MHz Reed Solomon gearbox */
|
||||
/* tx_desk_rsgb_pcs */
|
||||
644531250, /* 644.53125 MHz Reed Solomon gearbox */
|
||||
/* rx_desk_rsgb_pcs */
|
||||
644531250, /* 644.53125 MHz Reed Solomon gearbox */
|
||||
/* tx_fixed_delay */
|
||||
2095,
|
||||
/* pmd_adj_divisor */
|
||||
206250000,
|
||||
/* rx_fixed_delay */
|
||||
14524,
|
||||
},
|
||||
/* ICE_PTP_LNK_SPD_100G_RS */
|
||||
{
|
||||
/* tx_par_clk */
|
||||
0, /* unused */
|
||||
/* rx_par_clk */
|
||||
644531250, /* 644.53125 MHz */
|
||||
/* tx_pcs_clk */
|
||||
0, /* unused */
|
||||
/* rx_pcs_clk */
|
||||
644531250, /* 644.53125 MHz */
|
||||
/* tx_desk_rsgb_par */
|
||||
644531250, /* 644.53125 MHz Reed Solomon gearbox */
|
||||
/* rx_desk_rsgb_par */
|
||||
644531250, /* 644.53125 MHz Reed Solomon gearbox */
|
||||
/* tx_desk_rsgb_pcs */
|
||||
644531250, /* 644.53125 MHz Reed Solomon gearbox */
|
||||
/* rx_desk_rsgb_pcs */
|
||||
644531250, /* 644.53125 MHz Reed Solomon gearbox */
|
||||
/* tx_fixed_delay */
|
||||
1620,
|
||||
/* pmd_adj_divisor */
|
||||
206250000,
|
||||
/* rx_fixed_delay */
|
||||
7775,
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* _ICE_PTP_CONSTS_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -55,6 +55,44 @@ struct ice_time_ref_info_e822 {
|
||||
u8 pps_delay;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ice_vernier_info_e822
|
||||
* @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
|
||||
* @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
|
||||
* @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
|
||||
* @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
|
||||
* @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
|
||||
* @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
|
||||
* @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
|
||||
* @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
|
||||
* @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
|
||||
* @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
|
||||
* @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
|
||||
*
|
||||
* Table of constants used during as part of the Vernier calibration of the Tx
|
||||
* and Rx timestamps. This includes frequency values used to compute TUs per
|
||||
* PAR/PCS clock cycle, and static delay values measured during hardware
|
||||
* design.
|
||||
*
|
||||
* Note that some values are not used for all link speeds, and the
|
||||
* P_REG_DESK_PAR* registers may represent different clock markers at
|
||||
* different link speeds, either the deskew marker for multi-lane link speeds
|
||||
* or the Reed Solomon gearbox marker for RS-FEC.
|
||||
*/
|
||||
struct ice_vernier_info_e822 {
|
||||
u32 tx_par_clk;
|
||||
u32 rx_par_clk;
|
||||
u32 tx_pcs_clk;
|
||||
u32 rx_pcs_clk;
|
||||
u32 tx_desk_rsgb_par;
|
||||
u32 rx_desk_rsgb_par;
|
||||
u32 tx_desk_rsgb_pcs;
|
||||
u32 rx_desk_rsgb_pcs;
|
||||
u32 tx_fixed_delay;
|
||||
u32 pmd_adj_divisor;
|
||||
u32 rx_fixed_delay;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ice_cgu_pll_params_e822
|
||||
* @refclk_pre_div: Reference clock pre-divisor
|
||||
@ -78,6 +116,9 @@ ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
|
||||
/* Table of constants related to possible TIME_REF sources */
|
||||
extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
|
||||
|
||||
/* Table of constants for Vernier calibration on E822 */
|
||||
extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];
|
||||
|
||||
/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
|
||||
* the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
|
||||
*/
|
||||
@ -171,6 +212,12 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
|
||||
enum ice_ptp_link_spd *link_out,
|
||||
enum ice_ptp_fec_mode *fec_out);
|
||||
void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port);
|
||||
enum ice_status
|
||||
ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
|
||||
enum ice_status
|
||||
ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);
|
||||
enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
|
||||
enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
|
||||
|
||||
/* E810 family functions */
|
||||
enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user