net/ice/base: enable QinQ filter for switch advanced rule
Enable QinQ type filter for switch advanced rule, it support tunnel and non-tunnel packet use external and inner vlan id as input set for rules, it also support session id as input set for PPPoE rule with QinQ flag in packet. Signed-off-by: Wei Zhao <wei.zhao1@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Qiming Yang <qiming.yang@intel.com>
This commit is contained in:
Qi Zhang
Ferruh Yigit
parent
2906c7eac9
commit
ca5a25c5f0
@ -52,6 +52,7 @@ enum ice_protocol_type {
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ICE_AH,
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ICE_NAT_T,
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ICE_GTP_NO_PAY,
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ICE_VLAN_EX,
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ICE_PROTOCOL_LAST
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};
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@ -102,6 +103,12 @@ enum ice_sw_tunnel_type {
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ICE_SW_TUN_PROFID_IPV4_PFCP_SESSION,
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ICE_SW_TUN_PROFID_IPV6_PFCP_NODE,
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ICE_SW_TUN_PROFID_IPV6_PFCP_SESSION,
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ICE_SW_TUN_AND_NON_TUN_QINQ,
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ICE_NON_TUN_QINQ,
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ICE_SW_TUN_PPPOE_QINQ,
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ICE_SW_TUN_PPPOE_PAY_QINQ,
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ICE_SW_TUN_PPPOE_IPV4_QINQ,
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ICE_SW_TUN_PPPOE_IPV6_QINQ,
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ICE_ALL_TUNNELS /* All tunnel types including NVGRE */
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};
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@ -160,6 +167,7 @@ enum ice_prot_id {
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#define ICE_MAC_OFOS_HW 1
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#define ICE_MAC_IL_HW 4
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#define ICE_ETYPE_OL_HW 9
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#define ICE_VLAN_OF_HW 16
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#define ICE_VLAN_OL_HW 17
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#define ICE_IPV4_OFOS_HW 32
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#define ICE_IPV4_IL_HW 33
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@ -1202,6 +1202,153 @@ static const u8 dummy_ipv6_l2tpv3_pkt[] = {
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0x00, 0x00, /* 2 bytes for 4 bytes alignment */
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};
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static const struct ice_dummy_pkt_offsets dummy_qinq_ipv4_packet_offsets[] = {
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{ ICE_MAC_OFOS, 0 },
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{ ICE_VLAN_EX, 14 },
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{ ICE_VLAN_OFOS, 18 },
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{ ICE_IPV4_OFOS, 22 },
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{ ICE_PROTOCOL_LAST, 0 },
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};
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static const u8 dummy_qinq_ipv4_pkt[] = {
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0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x91, 0x00,
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0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */
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0x00, 0x00, 0x08, 0x00, /* ICE_VLAN_OFOS 18 */
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0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 22 */
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0x00, 0x01, 0x00, 0x00,
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0x00, 0x11, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 42 */
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0x00, 0x08, 0x00, 0x00,
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0x00, 0x00, /* 2 bytes for 4 byte alignment */
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};
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static const struct ice_dummy_pkt_offsets dummy_qinq_ipv6_packet_offsets[] = {
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{ ICE_MAC_OFOS, 0 },
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{ ICE_VLAN_EX, 14 },
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{ ICE_VLAN_OFOS, 18 },
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{ ICE_IPV6_OFOS, 22 },
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{ ICE_PROTOCOL_LAST, 0 },
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};
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static const u8 dummy_qinq_ipv6_pkt[] = {
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0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x91, 0x00,
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0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */
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0x00, 0x00, 0x86, 0xDD, /* ICE_VLAN_OFOS 18 */
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0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 22 */
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0x00, 0x10, 0x11, 0x00, /* Next header UDP */
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 62 */
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0x00, 0x10, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, /* needed for ESP packets */
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, /* 2 bytes for 4 byte alignment */
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};
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static const struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_offsets[] = {
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{ ICE_MAC_OFOS, 0 },
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{ ICE_VLAN_EX, 14 },
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{ ICE_VLAN_OFOS, 18 },
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{ ICE_PPPOE, 22 },
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{ ICE_PROTOCOL_LAST, 0 },
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};
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static const
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struct ice_dummy_pkt_offsets dummy_qinq_pppoe_ipv4_packet_offsets[] = {
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{ ICE_MAC_OFOS, 0 },
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{ ICE_VLAN_EX, 14 },
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{ ICE_VLAN_OFOS, 18 },
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{ ICE_PPPOE, 22 },
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{ ICE_IPV4_OFOS, 30 },
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{ ICE_PROTOCOL_LAST, 0 },
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};
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static const u8 dummy_qinq_pppoe_ipv4_pkt[] = {
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0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x91, 0x00,
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0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */
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0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 18 */
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0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */
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0x00, 0x16,
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0x00, 0x21, /* PPP Link Layer 28 */
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0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 30 */
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, /* 2 bytes for 4 byte alignment */
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};
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static const
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struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_ipv6_offsets[] = {
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{ ICE_MAC_OFOS, 0 },
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{ ICE_ETYPE_OL, 12 },
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{ ICE_VLAN_EX, 14},
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{ ICE_VLAN_OFOS, 18 },
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{ ICE_PPPOE, 22 },
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{ ICE_IPV6_OFOS, 30 },
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{ ICE_PROTOCOL_LAST, 0 },
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};
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static const u8 dummy_qinq_pppoe_ipv6_packet[] = {
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0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x91, 0x00, /* ICE_ETYPE_OL 12 */
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0x00, 0x00, 0x81, 0x00, /* ICE_VLAN_EX 14 */
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0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 18 */
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0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */
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0x00, 0x2a,
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0x00, 0x57, /* PPP Link Layer 28*/
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0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 30 */
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0x00, 0x00, 0x3b, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, /* 2 bytes for 4 bytes alignment */
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};
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/* this is a recipe to profile association bitmap */
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static ice_declare_bitmap(recipe_to_profile[ICE_MAX_NUM_RECIPES],
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ICE_MAX_NUM_PROFILES);
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@ -1229,13 +1376,13 @@ static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,
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* ice_get_tun_type_for_recipe - get tunnel type for the recipe
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* @rid: recipe ID that we are populating
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*/
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static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid)
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static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid, bool vlan)
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{
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u8 vxlan_profile[12] = {10, 11, 12, 16, 17, 18, 22, 23, 24, 25, 26, 27};
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u8 gre_profile[12] = {13, 14, 15, 19, 20, 21, 28, 29, 30, 31, 32, 33};
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u8 pppoe_profile[7] = {34, 35, 36, 37, 38, 39, 40};
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u8 non_tun_profile[6] = {4, 5, 6, 7, 8, 9};
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enum ice_sw_tunnel_type tun_type = ICE_NON_TUN;
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enum ice_sw_tunnel_type tun_type;
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u16 i, j, profile_num = 0;
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bool non_tun_valid = false;
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bool pppoe_valid = false;
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@ -1416,6 +1563,19 @@ static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid)
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}
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}
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if (vlan && tun_type == ICE_SW_TUN_PPPOE)
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tun_type = ICE_SW_TUN_PPPOE_QINQ;
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else if (vlan && tun_type == ICE_SW_TUN_PPPOE_IPV6)
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tun_type = ICE_SW_TUN_PPPOE_IPV6_QINQ;
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else if (vlan && tun_type == ICE_SW_TUN_PPPOE_IPV4)
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tun_type = ICE_SW_TUN_PPPOE_IPV4_QINQ;
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else if (vlan && tun_type == ICE_SW_TUN_PPPOE_PAY)
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tun_type = ICE_SW_TUN_PPPOE_PAY_QINQ;
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else if (vlan && tun_type == ICE_SW_TUN_AND_NON_TUN)
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tun_type = ICE_SW_TUN_AND_NON_TUN_QINQ;
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else if (vlan && tun_type == ICE_NON_TUN)
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tun_type = ICE_NON_TUN_QINQ;
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return tun_type;
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}
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@ -1440,6 +1600,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
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struct ice_prot_lkup_ext *lkup_exts;
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enum ice_status status;
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u8 fv_word_idx = 0;
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bool vlan = false;
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u16 sub_recps;
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ice_zero_bitmap(result_bm, ICE_MAX_FV_WORDS);
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@ -1528,6 +1689,9 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
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lkup_exts->fv_words[fv_word_idx].off = off;
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lkup_exts->field_mask[fv_word_idx] =
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rg_entry->fv_mask[i];
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if (prot == ICE_META_DATA_ID_HW &&
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off == ICE_TUN_FLAG_MDID_OFF)
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vlan = true;
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fv_word_idx++;
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}
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/* populate rg_list with the data from the child entry of this
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@ -1562,7 +1726,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
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lkup_exts->n_val_words = fv_word_idx;
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recps[rid].big_recp = (num_recps > 1);
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recps[rid].n_grp_count = (u8)num_recps;
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recps[rid].tun_type = ice_get_tun_type_for_recipe(rid);
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recps[rid].tun_type = ice_get_tun_type_for_recipe(rid, vlan);
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recps[rid].root_buf = (struct ice_aqc_recipe_data_elem *)
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ice_memdup(hw, tmp, recps[rid].n_grp_count *
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sizeof(*recps[rid].root_buf), ICE_NONDMA_TO_NONDMA);
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@ -2726,7 +2890,7 @@ enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw)
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} while (req_desc && !status);
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out:
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ice_free(hw, (void *)rbuf);
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ice_free(hw, rbuf);
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return status;
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}
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@ -2982,8 +3146,7 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,
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m_ent->fltr_info.fwd_id.hw_vsi_id;
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act = ICE_LG_ACT_VSI_FORWARDING | ICE_LG_ACT_VALID_BIT;
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act |= (id << ICE_LG_ACT_VSI_LIST_ID_S) &
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ICE_LG_ACT_VSI_LIST_ID_M;
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act |= (id << ICE_LG_ACT_VSI_LIST_ID_S) & ICE_LG_ACT_VSI_LIST_ID_M;
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if (m_ent->vsi_count > 1)
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act |= ICE_LG_ACT_VSI_LIST;
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lg_act->pdata.lg_act.act[0] = CPU_TO_LE32(act);
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@ -3064,13 +3227,11 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,
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*/
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lg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(num_acts);
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rules_size = lg_act_size + ICE_SW_RULE_RX_TX_ETH_HDR_SIZE;
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lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw,
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rules_size);
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lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size);
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if (!lg_act)
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return ICE_ERR_NO_MEMORY;
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rx_tx = (struct ice_aqc_sw_rules_elem *)
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((u8 *)lg_act + lg_act_size);
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rx_tx = (struct ice_aqc_sw_rules_elem *)((u8 *)lg_act + lg_act_size);
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/* Fill in the first switch rule i.e. large action */
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lg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);
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@ -4525,7 +4686,8 @@ ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set,
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hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
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s_rule_size = set ? ICE_SW_RULE_RX_TX_ETH_HDR_SIZE :
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ICE_SW_RULE_RX_TX_NO_HDR_SIZE;
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ICE_SW_RULE_RX_TX_NO_HDR_SIZE;
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s_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size);
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if (!s_rule)
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return ICE_ERR_NO_MEMORY;
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@ -5825,6 +5987,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[ICE_PROTOCOL_LAST] = {
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{ ICE_AH, { 0, 2, 4, 6, 8, 10 } },
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{ ICE_NAT_T, { 8, 10, 12, 14 } },
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{ ICE_GTP_NO_PAY, { 8, 10, 12, 14 } },
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{ ICE_VLAN_EX, { 0, 2 } },
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};
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/* The following table describes preferred grouping of recipes.
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@ -5858,6 +6021,7 @@ static const struct ice_protocol_entry ice_prot_id_tbl[ICE_PROTOCOL_LAST] = {
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{ ICE_AH, ICE_AH_HW },
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{ ICE_NAT_T, ICE_UDP_ILOS_HW },
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{ ICE_GTP_NO_PAY, ICE_UDP_ILOS_HW },
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{ ICE_VLAN_EX, ICE_VLAN_OF_HW },
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};
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/**
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@ -6569,6 +6733,12 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *mask)
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case ICE_SW_TUN_NVGRE:
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case ICE_SW_TUN_UDP:
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case ICE_ALL_TUNNELS:
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case ICE_SW_TUN_AND_NON_TUN_QINQ:
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case ICE_NON_TUN_QINQ:
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case ICE_SW_TUN_PPPOE_QINQ:
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case ICE_SW_TUN_PPPOE_PAY_QINQ:
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case ICE_SW_TUN_PPPOE_IPV4_QINQ:
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case ICE_SW_TUN_PPPOE_IPV6_QINQ:
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*mask = ICE_TUN_FLAG_MASK;
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return true;
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@ -6627,6 +6797,7 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,
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switch (rinfo->tun_type) {
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case ICE_NON_TUN:
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case ICE_NON_TUN_QINQ:
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prof_type = ICE_PROF_NON_TUN;
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break;
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case ICE_ALL_TUNNELS:
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@ -6645,12 +6816,15 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,
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prof_type = ICE_PROF_TUN_GRE;
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break;
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case ICE_SW_TUN_PPPOE:
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case ICE_SW_TUN_PPPOE_QINQ:
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prof_type = ICE_PROF_TUN_PPPOE;
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break;
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case ICE_SW_TUN_PPPOE_PAY:
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case ICE_SW_TUN_PPPOE_PAY_QINQ:
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ice_set_bit(ICE_PROFID_PPPOE_PAY, bm);
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return;
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case ICE_SW_TUN_PPPOE_IPV4:
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case ICE_SW_TUN_PPPOE_IPV4_QINQ:
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ice_set_bit(ICE_PROFID_PPPOE_IPV4_OTHER, bm);
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ice_set_bit(ICE_PROFID_PPPOE_IPV4_UDP, bm);
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ice_set_bit(ICE_PROFID_PPPOE_IPV4_TCP, bm);
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@ -6662,6 +6836,7 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,
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ice_set_bit(ICE_PROFID_PPPOE_IPV4_UDP, bm);
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return;
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case ICE_SW_TUN_PPPOE_IPV6:
|
||||
case ICE_SW_TUN_PPPOE_IPV6_QINQ:
|
||||
ice_set_bit(ICE_PROFID_PPPOE_IPV6_OTHER, bm);
|
||||
ice_set_bit(ICE_PROFID_PPPOE_IPV6_UDP, bm);
|
||||
ice_set_bit(ICE_PROFID_PPPOE_IPV6_TCP, bm);
|
||||
@ -6757,6 +6932,7 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,
|
||||
ice_set_bit(ICE_PROFID_IPV6_GTPU_IPV6_TCP, bm);
|
||||
return;
|
||||
case ICE_SW_TUN_AND_NON_TUN:
|
||||
case ICE_SW_TUN_AND_NON_TUN_QINQ:
|
||||
default:
|
||||
prof_type = ICE_PROF_ALL;
|
||||
break;
|
||||
@ -7046,6 +7222,38 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
|
||||
tcp = true;
|
||||
}
|
||||
|
||||
if ((tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||
|
||||
tun_type == ICE_NON_TUN_QINQ) && ipv6) {
|
||||
*pkt = dummy_qinq_ipv6_pkt;
|
||||
*pkt_len = sizeof(dummy_qinq_ipv6_pkt);
|
||||
*offsets = dummy_qinq_ipv6_packet_offsets;
|
||||
return;
|
||||
} else if (tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||
|
||||
tun_type == ICE_NON_TUN_QINQ) {
|
||||
*pkt = dummy_qinq_ipv4_pkt;
|
||||
*pkt_len = sizeof(dummy_qinq_ipv4_pkt);
|
||||
*offsets = dummy_qinq_ipv4_packet_offsets;
|
||||
return;
|
||||
}
|
||||
|
||||
if (tun_type == ICE_SW_TUN_PPPOE_IPV6_QINQ) {
|
||||
*pkt = dummy_qinq_pppoe_ipv6_packet;
|
||||
*pkt_len = sizeof(dummy_qinq_pppoe_ipv6_packet);
|
||||
*offsets = dummy_qinq_pppoe_packet_ipv6_offsets;
|
||||
return;
|
||||
} else if (tun_type == ICE_SW_TUN_PPPOE_IPV4_QINQ) {
|
||||
*pkt = dummy_qinq_pppoe_ipv4_pkt;
|
||||
*pkt_len = sizeof(dummy_qinq_pppoe_ipv4_pkt);
|
||||
*offsets = dummy_qinq_pppoe_ipv4_packet_offsets;
|
||||
return;
|
||||
} else if (tun_type == ICE_SW_TUN_PPPOE_QINQ ||
|
||||
tun_type == ICE_SW_TUN_PPPOE_PAY_QINQ) {
|
||||
*pkt = dummy_qinq_pppoe_ipv4_pkt;
|
||||
*pkt_len = sizeof(dummy_qinq_pppoe_ipv4_pkt);
|
||||
*offsets = dummy_qinq_pppoe_packet_offsets;
|
||||
return;
|
||||
}
|
||||
|
||||
if (tun_type == ICE_SW_TUN_IPV4_GTPU_NO_PAY) {
|
||||
*pkt = dummy_ipv4_gtpu_ipv4_packet;
|
||||
*pkt_len = sizeof(dummy_ipv4_gtpu_ipv4_packet);
|
||||
@ -7364,6 +7572,7 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
|
||||
len = sizeof(struct ice_ethtype_hdr);
|
||||
break;
|
||||
case ICE_VLAN_OFOS:
|
||||
case ICE_VLAN_EX:
|
||||
len = sizeof(struct ice_vlan_hdr);
|
||||
break;
|
||||
case ICE_IPV4_OFOS:
|
||||
@ -8038,9 +8247,8 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
|
||||
u16 rule_buf_sz;
|
||||
|
||||
rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE;
|
||||
s_rule =
|
||||
(struct ice_aqc_sw_rules_elem *)ice_malloc(hw,
|
||||
rule_buf_sz);
|
||||
s_rule = (struct ice_aqc_sw_rules_elem *)
|
||||
ice_malloc(hw, rule_buf_sz);
|
||||
if (!s_rule)
|
||||
return ICE_ERR_NO_MEMORY;
|
||||
s_rule->pdata.lkup_tx_rx.act = 0;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user