crypto/cnxk: update capabilities as per firmware
Updated CPT engine capabilities structure as per microcode. Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
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@ -1523,7 +1523,10 @@ union cpt_eng_caps {
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uint64_t __io kasumi : 1;
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uint64_t __io des : 1;
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uint64_t __io crc : 1;
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uint64_t __io reserved_14_63 : 50;
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uint64_t __io mmul : 1;
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uint64_t __io reserved_15_33 : 19;
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uint64_t __io pdcp_chain : 1;
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uint64_t __io reserved_35_63 : 29;
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};
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};
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@ -449,9 +449,7 @@ cnxk_sess_fill(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xform,
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bool pdcp_chain_supported = false;
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bool ciph_then_auth = false;
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if (roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_96XX_B0 ||
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roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_96XX_C0 ||
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roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_98XX)
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if (roc_cpt->hw_caps[CPT_ENG_TYPE_SE].pdcp_chain)
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pdcp_chain_supported = true;
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if (xform == NULL)
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