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net/ice/base: use macro instead of open-coded division

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For some operating systems, 64-bit division requires using specific
implementations. Use the DIV_64BIT macro to replace open-coded division
so that the driver may convert this to the appropriate operating-system
specific implementation when necessary.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
This commit is contained in:
Qi Zhang 2021-09-16 17:52:55 +08:00
parent 8d90c55c45
commit cb9c171a24
1 changed files with 32 additions and 21 deletions
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53
drivers/net/ice/base/ice_ptp_hw.c
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@ -1634,7 +1634,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
#define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
/* Program the 10Gb/40Gb conversion ratio */
uix = (tu_per_sec * LINE_UI_10G_40G) / 390625000;
uix = DIV_64BIT(tu_per_sec * LINE_UI_10G_40G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
uix);
@ -1645,7 +1645,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
}
/* Program the 25Gb/100Gb conversion ratio */
uix = (tu_per_sec * LINE_UI_25G_100G) / 390625000;
uix = DIV_64BIT(tu_per_sec * LINE_UI_25G_100G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
uix);
@ -1727,7 +1727,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_par_clk)
phy_tus = tu_per_sec / e822_vernier[link_spd].tx_par_clk;
phy_tus = DIV_64BIT(tu_per_sec,
e822_vernier[link_spd].tx_par_clk);
else
phy_tus = 0;
@ -1738,7 +1739,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_par_clk)
phy_tus = tu_per_sec / e822_vernier[link_spd].rx_par_clk;
phy_tus = DIV_64BIT(tu_per_sec,
e822_vernier[link_spd].rx_par_clk);
else
phy_tus = 0;
@ -1749,7 +1751,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_pcs_clk)
phy_tus = tu_per_sec / e822_vernier[link_spd].tx_pcs_clk;
phy_tus = DIV_64BIT(tu_per_sec,
e822_vernier[link_spd].tx_pcs_clk);
else
phy_tus = 0;
@ -1760,7 +1763,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_pcs_clk)
phy_tus = tu_per_sec / e822_vernier[link_spd].rx_pcs_clk;
phy_tus = DIV_64BIT(tu_per_sec,
e822_vernier[link_spd].rx_pcs_clk);
else
phy_tus = 0;
@ -1771,7 +1775,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_par)
phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_par;
phy_tus = DIV_64BIT(tu_per_sec,
e822_vernier[link_spd].tx_desk_rsgb_par);
else
phy_tus = 0;
@ -1782,7 +1787,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_desk_rsgb_par)
phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_par;
phy_tus = DIV_64BIT(tu_per_sec,
e822_vernier[link_spd].rx_desk_rsgb_par);
else
phy_tus = 0;
@ -1793,7 +1799,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_pcs;
phy_tus = DIV_64BIT(tu_per_sec,
e822_vernier[link_spd].tx_desk_rsgb_pcs);
else
phy_tus = 0;
@ -1804,7 +1811,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_pcs;
phy_tus = DIV_64BIT(tu_per_sec,
e822_vernier[link_spd].rx_desk_rsgb_pcs);
else
phy_tus = 0;
@ -1836,9 +1844,9 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
* overflows 64 bit integer arithmetic, so break it up into two
* divisions by 1e4 first then by 1e7.
*/
fixed_offset = tu_per_sec / 10000;
fixed_offset = DIV_64BIT(tu_per_sec, 10000);
fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
fixed_offset /= 10000000;
fixed_offset = DIV_64BIT(fixed_offset, 10000000);
return fixed_offset;
}
@ -1982,9 +1990,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
{
u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
u32 pmd_adj_divisor, val;
enum ice_status status;
u8 pmd_align;
u32 val;
status = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);
if (status) {
@ -2001,6 +2009,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
/* Calculate TUs per second */
tu_per_sec = cur_freq * clk_incval;
/* Get the link speed dependent PMD adjustment divisor */
pmd_adj_divisor = e822_vernier[link_spd].pmd_adj_divisor;
/* The PMD alignment adjustment measurement depends on the link speed,
* and whether FEC is enabled. For each link speed, the alignment
* adjustment is calculated by dividing a value by the length of
@ -2063,9 +2074,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
* divide by 125, and then handle remaining divisor based on the link
* speed pmd_adj_divisor value.
*/
adj = tu_per_sec / 125;
adj = DIV_64BIT(tu_per_sec, 125);
adj *= mult;
adj /= e822_vernier[link_spd].pmd_adj_divisor;
adj = DIV_64BIT(adj, pmd_adj_divisor);
/* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
* cycle count is necessary.
@ -2086,9 +2097,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
if (rx_cycle) {
mult = (4 - rx_cycle) * 40;
cycle_adj = tu_per_sec / 125;
cycle_adj = DIV_64BIT(tu_per_sec, 125);
cycle_adj *= mult;
cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
cycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);
adj += cycle_adj;
}
@ -2108,9 +2119,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
if (rx_cycle) {
mult = rx_cycle * 40;
cycle_adj = tu_per_sec / 125;
cycle_adj = DIV_64BIT(tu_per_sec, 125);
cycle_adj *= mult;
cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
cycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);
adj += cycle_adj;
}
@ -2146,9 +2157,9 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
* overflows 64 bit integer arithmetic, so break it up into two
* divisions by 1e4 first then by 1e7.
*/
fixed_offset = tu_per_sec / 10000;
fixed_offset = DIV_64BIT(tu_per_sec, 10000);
fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
fixed_offset /= 10000000;
fixed_offset = DIV_64BIT(fixed_offset, 10000000);
return fixed_offset;
}