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lpm/arm: support NEON

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Enabled CONFIG_RTE_LIBRTE_LPM, CONFIG_RTE_LIBRTE_TABLE,
CONFIG_RTE_LIBRTE_PIPELINE libraries for arm and arm64

TABLE, PIPELINE libraries were disabled due to LPM library dependency.

Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Signed-off-by: Jianbo Liu <jianbo.liu@linaro.org>
This commit is contained in:
Jerin Jacob 2016-03-11 09:22:58 +05:30 committed by Thomas Monjalon
parent 15d8dfc05b
commit cbc2f1dccf
7 changed files with 183 additions and 6 deletions
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1
MAINTAINERS
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@ -139,6 +139,7 @@ M: Jerin Jacob <jerin.jacob@caviumnetworks.com>
M: Jianbo Liu <jianbo.liu@linaro.org>
F: lib/librte_eal/common/include/arch/arm/*_64.h
F: lib/librte_acl/acl_run_neon.*
F: lib/librte_lpm/rte_lpm_neon.h
EZchip TILE-Gx
M: Zhigang Lu <zlu@ezchip.com>

20
app/test/test_xmmt_ops.h
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@ -36,6 +36,24 @@
#include <rte_vect.h>
#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64)
/* vect_* abstraction implementation using NEON */
/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
#define vect_loadu_sil128(p) vld1q_s32((const int32_t *)p)
/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
static inline xmm_t __attribute__((always_inline))
vect_set_epi32(int i3, int i2, int i1, int i0)
{
int32_t data[4] = {i0, i1, i2, i3};
return vld1q_s32(data);
}
#elif defined(RTE_ARCH_X86)
/* vect_* abstraction implementation using SSE */
/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
@ -44,4 +62,6 @@
/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
#define vect_set_epi32(i3, i2, i1, i0) _mm_set_epi32(i3, i2, i1, i0)
#endif
#endif /* _TEST_XMMT_OPS_H_ */

3
config/defconfig_arm-armv7a-linuxapp-gcc
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@ -54,9 +54,6 @@ CONFIG_RTE_LIBRTE_KNI=n
CONFIG_RTE_EAL_IGB_UIO=n
# fails to compile on ARM
CONFIG_RTE_LIBRTE_LPM=n
CONFIG_RTE_LIBRTE_TABLE=n
CONFIG_RTE_LIBRTE_PIPELINE=n
CONFIG_RTE_SCHED_VECTOR=n
# cannot use those on ARM

3
config/defconfig_arm64-armv8a-linuxapp-gcc
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@ -48,7 +48,4 @@ CONFIG_RTE_LIBRTE_IVSHMEM=n
CONFIG_RTE_LIBRTE_FM10K_PMD=n
CONFIG_RTE_LIBRTE_I40E_PMD=n
CONFIG_RTE_LIBRTE_LPM=n
CONFIG_RTE_LIBRTE_TABLE=n
CONFIG_RTE_LIBRTE_PIPELINE=n
CONFIG_RTE_SCHED_VECTOR=n

5
lib/librte_lpm/Makefile
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@ -46,7 +46,12 @@ SRCS-$(CONFIG_RTE_LIBRTE_LPM) := rte_lpm.c rte_lpm6.c
# install this header file
SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include := rte_lpm.h rte_lpm6.h
ifneq ($(filter y,$(CONFIG_RTE_ARCH_ARM) $(CONFIG_RTE_ARCH_ARM64)),)
SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include += rte_lpm_neon.h
else ifeq ($(CONFIG_RTE_ARCH_X86),y)
SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include += rte_lpm_sse.h
endif
# this lib needs eal
DEPDIRS-$(CONFIG_RTE_LIBRTE_LPM) += lib/librte_eal

4
lib/librte_lpm/rte_lpm.h
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@ -478,7 +478,11 @@ static inline void
rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
uint32_t defv);
#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64)
#include "rte_lpm_neon.h"
#else
#include "rte_lpm_sse.h"
#endif
#ifdef __cplusplus
}

153
lib/librte_lpm/rte_lpm_neon.h Normal file
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@ -0,0 +1,153 @@
/*-
* BSD LICENSE
*
* Copyright(c) 2015 Cavium Networks. All rights reserved.
* All rights reserved.
*
* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Derived rte_lpm_lookupx4 implementation from lib/librte_lpm/rte_lpm_sse.h
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Cavium Networks nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _RTE_LPM_NEON_H_
#define _RTE_LPM_NEON_H_
#include <rte_branch_prediction.h>
#include <rte_byteorder.h>
#include <rte_common.h>
#include <rte_vect.h>
#ifdef __cplusplus
extern "C" {
#endif
static inline void
rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
uint32_t defv)
{
uint32x4_t i24;
rte_xmm_t i8;
uint32_t tbl[4];
uint64_t idx, pt, pt2;
const uint32_t *ptbl;
const uint32_t mask = UINT8_MAX;
const int32x4_t mask8 = vdupq_n_s32(mask);
/*
* RTE_LPM_VALID_EXT_ENTRY_BITMASK for 2 LPM entries
* as one 64-bit value (0x0300000003000000).
*/
const uint64_t mask_xv =
((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK |
(uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32);
/*
* RTE_LPM_LOOKUP_SUCCESS for 2 LPM entries
* as one 64-bit value (0x0100000001000000).
*/
const uint64_t mask_v =
((uint64_t)RTE_LPM_LOOKUP_SUCCESS |
(uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32);
/* get 4 indexes for tbl24[]. */
i24 = vshrq_n_u32((uint32x4_t)ip, CHAR_BIT);
/* extract values from tbl24[] */
idx = vgetq_lane_u64((uint64x2_t)i24, 0);
ptbl = (const uint32_t *)&lpm->tbl24[(uint32_t)idx];
tbl[0] = *ptbl;
ptbl = (const uint32_t *)&lpm->tbl24[idx >> 32];
tbl[1] = *ptbl;
idx = vgetq_lane_u64((uint64x2_t)i24, 1);
ptbl = (const uint32_t *)&lpm->tbl24[(uint32_t)idx];
tbl[2] = *ptbl;
ptbl = (const uint32_t *)&lpm->tbl24[idx >> 32];
tbl[3] = *ptbl;
/* get 4 indexes for tbl8[]. */
i8.x = vandq_s32(ip, mask8);
pt = (uint64_t)tbl[0] |
(uint64_t)tbl[1] << 32;
pt2 = (uint64_t)tbl[2] |
(uint64_t)tbl[3] << 32;
/* search successfully finished for all 4 IP addresses. */
if (likely((pt & mask_xv) == mask_v) &&
likely((pt2 & mask_xv) == mask_v)) {
*(uint64_t *)hop = pt & RTE_LPM_MASKX4_RES;
*(uint64_t *)(hop + 2) = pt2 & RTE_LPM_MASKX4_RES;
return;
}
if (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
i8.u32[0] = i8.u32[0] +
(uint8_t)tbl[0] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[0]];
tbl[0] = *ptbl;
}
if (unlikely((pt >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
i8.u32[1] = i8.u32[1] +
(uint8_t)tbl[1] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[1]];
tbl[1] = *ptbl;
}
if (unlikely((pt2 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
i8.u32[2] = i8.u32[2] +
(uint8_t)tbl[2] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[2]];
tbl[2] = *ptbl;
}
if (unlikely((pt2 >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
i8.u32[3] = i8.u32[3] +
(uint8_t)tbl[3] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[3]];
tbl[3] = *ptbl;
}
hop[0] = (tbl[0] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[0] & 0x00FFFFFF : defv;
hop[1] = (tbl[1] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[1] & 0x00FFFFFF : defv;
hop[2] = (tbl[2] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[2] & 0x00FFFFFF : defv;
hop[3] = (tbl[3] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[3] & 0x00FFFFFF : defv;
}
#ifdef __cplusplus
}
#endif
#endif /* _RTE_LPM_NEON_H_ */