net/txgbe: support priority flow control
Add priority flow control support. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Jiawen Wu
Ferruh Yigit
parent
4fb0ef9562
commit
cc389e5109
@ -7,6 +7,146 @@
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#include "txgbe_dcb.h"
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#include "txgbe_dcb_hw.h"
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/**
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* txgbe_pfc_enable - Enable flow control
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* @hw: pointer to hardware structure
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* @tc_num: traffic class number
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* Enable flow control according to the current settings.
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*/
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int
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txgbe_dcb_pfc_enable(struct txgbe_hw *hw, uint8_t tc_num)
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{
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int ret_val = 0;
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uint32_t mflcn_reg, fccfg_reg;
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uint32_t pause_time;
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uint32_t fcrtl, fcrth;
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uint8_t i;
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uint8_t nb_rx_en;
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/* Validate the water mark configuration */
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if (!hw->fc.pause_time) {
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ret_val = TXGBE_ERR_INVALID_LINK_SETTINGS;
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goto out;
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}
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/* Low water mark of zero causes XOFF floods */
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if (hw->fc.current_mode & txgbe_fc_tx_pause) {
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/* High/Low water can not be 0 */
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if (!hw->fc.high_water[tc_num] ||
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!hw->fc.low_water[tc_num]) {
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PMD_INIT_LOG(ERR, "Invalid water mark configuration");
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ret_val = TXGBE_ERR_INVALID_LINK_SETTINGS;
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goto out;
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}
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if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
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PMD_INIT_LOG(ERR, "Invalid water mark configuration");
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ret_val = TXGBE_ERR_INVALID_LINK_SETTINGS;
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goto out;
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}
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}
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/* Negotiate the fc mode to use */
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txgbe_fc_autoneg(hw);
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/* Disable any previous flow control settings */
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mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
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mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);
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fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
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fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);
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switch (hw->fc.current_mode) {
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case txgbe_fc_none:
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/*
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* If the count of enabled RX Priority Flow control > 1,
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* and the TX pause can not be disabled
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*/
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nb_rx_en = 0;
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for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
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uint32_t reg = rd32(hw, TXGBE_FCWTRHI(i));
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if (reg & TXGBE_FCWTRHI_XOFF)
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nb_rx_en++;
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}
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if (nb_rx_en > 1)
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fccfg_reg |= TXGBE_TXFCCFG_PFC;
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break;
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case txgbe_fc_rx_pause:
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/*
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* Rx Flow control is enabled and Tx Flow control is
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* disabled by software override. Since there really
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* isn't a way to advertise that we are capable of RX
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* Pause ONLY, we will advertise that we support both
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* symmetric and asymmetric Rx PAUSE. Later, we will
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* disable the adapter's ability to send PAUSE frames.
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*/
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mflcn_reg |= TXGBE_RXFCCFG_PFC;
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/*
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* If the count of enabled RX Priority Flow control > 1,
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* and the TX pause can not be disabled
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*/
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nb_rx_en = 0;
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for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
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uint32_t reg = rd32(hw, TXGBE_FCWTRHI(i));
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if (reg & TXGBE_FCWTRHI_XOFF)
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nb_rx_en++;
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}
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if (nb_rx_en > 1)
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fccfg_reg |= TXGBE_TXFCCFG_PFC;
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break;
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case txgbe_fc_tx_pause:
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/*
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* Tx Flow control is enabled, and Rx Flow control is
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* disabled by software override.
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*/
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fccfg_reg |= TXGBE_TXFCCFG_PFC;
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break;
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case txgbe_fc_full:
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/* Flow control (both Rx and Tx) is enabled by SW override. */
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mflcn_reg |= TXGBE_RXFCCFG_PFC;
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fccfg_reg |= TXGBE_TXFCCFG_PFC;
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break;
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default:
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PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
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ret_val = TXGBE_ERR_CONFIG;
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goto out;
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}
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/* Set 802.3x based flow control settings. */
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wr32(hw, TXGBE_RXFCCFG, mflcn_reg);
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wr32(hw, TXGBE_TXFCCFG, fccfg_reg);
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/* Set up and enable Rx high/low water mark thresholds, enable XON. */
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if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
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hw->fc.high_water[tc_num]) {
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fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[tc_num]) |
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TXGBE_FCWTRLO_XON;
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fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[tc_num]) |
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TXGBE_FCWTRHI_XOFF;
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} else {
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/*
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* In order to prevent Tx hangs when the internal Tx
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* switch is enabled we must set the high water mark
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* to the maximum FCRTH value. This allows the Tx
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* switch to function even under heavy Rx workloads.
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*/
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fcrtl = 0;
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fcrth = rd32(hw, TXGBE_PBRXSIZE(tc_num)) - 32;
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}
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wr32(hw, TXGBE_FCWTRLO(tc_num), fcrtl);
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wr32(hw, TXGBE_FCWTRHI(tc_num), fcrth);
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/* Configure pause time (2 TCs per register) */
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pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);
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for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
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wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);
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/* Configure flow control refresh threshold value */
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wr32(hw, TXGBE_RXFCRFSH, pause_time / 2);
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out:
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return ret_val;
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}
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/**
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* txgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
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* @hw: pointer to hardware structure
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@ -210,3 +350,11 @@ void txgbe_dcb_unpack_map_cee(struct txgbe_dcb_config *cfg, int direction,
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map[up] = txgbe_dcb_get_tc_from_up(cfg, direction, up);
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}
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/* Helper routines to abstract HW specifics from DCB netlink ops */
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s32 txgbe_dcb_config_pfc(struct txgbe_hw *hw, u8 pfc_en, u8 *map)
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{
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int ret = TXGBE_ERR_PARAM;
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ret = txgbe_dcb_config_pfc_raptor(hw, pfc_en, map);
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return ret;
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}
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@ -92,6 +92,8 @@ struct txgbe_dcb_config {
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bool vt_mode;
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};
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int txgbe_dcb_pfc_enable(struct txgbe_hw *hw, u8 tc_num);
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/* DCB credits calculation */
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s32 txgbe_dcb_calculate_tc_credits_cee(struct txgbe_hw *hw,
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struct txgbe_dcb_config *dcb_config,
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@ -180,6 +180,79 @@ s32 txgbe_dcb_config_tx_data_arbiter_raptor(struct txgbe_hw *hw, u16 *refill,
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return 0;
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}
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/**
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* txgbe_dcb_config_pfc_raptor - Configure priority flow control
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* @hw: pointer to hardware structure
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* @pfc_en: enabled pfc bitmask
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* @map: priority to tc assignments indexed by priority
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*
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* Configure Priority Flow Control (PFC) for each traffic class.
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*/
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s32 txgbe_dcb_config_pfc_raptor(struct txgbe_hw *hw, u8 pfc_en, u8 *map)
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{
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u32 i, j, fcrtl, reg;
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u8 max_tc = 0;
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/* Enable Transmit Priority Flow Control */
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wr32(hw, TXGBE_TXFCCFG, TXGBE_TXFCCFG_PFC);
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/* Enable Receive Priority Flow Control */
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wr32m(hw, TXGBE_RXFCCFG, TXGBE_RXFCCFG_PFC,
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pfc_en ? TXGBE_RXFCCFG_PFC : 0);
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for (i = 0; i < TXGBE_DCB_UP_MAX; i++) {
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if (map[i] > max_tc)
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max_tc = map[i];
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}
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/* Configure PFC Tx thresholds per TC */
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for (i = 0; i <= max_tc; i++) {
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int enabled = 0;
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for (j = 0; j < TXGBE_DCB_UP_MAX; j++) {
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if (map[j] == i && (pfc_en & (1 << j))) {
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enabled = 1;
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break;
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}
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}
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if (enabled) {
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reg = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
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TXGBE_FCWTRHI_XOFF;
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fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
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TXGBE_FCWTRLO_XON;
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wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
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} else {
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/*
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* In order to prevent Tx hangs when the internal Tx
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* switch is enabled we must set the high water mark
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* to the Rx packet buffer size - 24KB. This allows
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* the Tx switch to function even under heavy Rx
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* workloads.
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*/
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reg = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
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wr32(hw, TXGBE_FCWTRLO(i), 0);
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}
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wr32(hw, TXGBE_FCWTRHI(i), reg);
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}
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for (; i < TXGBE_DCB_TC_MAX; i++) {
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wr32(hw, TXGBE_FCWTRLO(i), 0);
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wr32(hw, TXGBE_FCWTRHI(i), 0);
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}
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/* Configure pause time (2 TCs per register) */
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reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
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for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
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wr32(hw, TXGBE_FCXOFFTM(i), reg);
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/* Configure flow control refresh threshold value */
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wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
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return 0;
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}
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/**
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* txgbe_dcb_config_tc_stats_raptor - Config traffic class statistics
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* @hw: pointer to hardware structure
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@ -2799,6 +2799,59 @@ txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
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return -EIO;
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}
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static int
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txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
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struct rte_eth_pfc_conf *pfc_conf)
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{
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int err;
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uint32_t rx_buf_size;
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uint32_t max_high_water;
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uint8_t tc_num;
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uint8_t map[TXGBE_DCB_UP_MAX] = { 0 };
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struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
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struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
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enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
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txgbe_fc_none,
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txgbe_fc_rx_pause,
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txgbe_fc_tx_pause,
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txgbe_fc_full
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};
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PMD_INIT_FUNC_TRACE();
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txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
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tc_num = map[pfc_conf->priority];
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rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
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PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
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/*
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* At least reserve one Ethernet frame for watermark
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* high_water/low_water in kilo bytes for txgbe
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*/
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max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
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if (pfc_conf->fc.high_water > max_high_water ||
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pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
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PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
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PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
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return -EINVAL;
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}
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hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
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hw->fc.pause_time = pfc_conf->fc.pause_time;
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hw->fc.send_xon = pfc_conf->fc.send_xon;
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hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
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hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
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err = txgbe_dcb_pfc_enable(hw, tc_num);
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/* Not negotiated is not an error case */
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if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
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return 0;
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PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
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return -EIO;
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}
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int
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txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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@ -3286,6 +3339,7 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {
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.tx_queue_release = txgbe_dev_tx_queue_release,
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.flow_ctrl_get = txgbe_flow_ctrl_get,
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.flow_ctrl_set = txgbe_flow_ctrl_set,
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.priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set,
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.mac_addr_add = txgbe_add_rar,
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.mac_addr_remove = txgbe_remove_rar,
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.mac_addr_set = txgbe_set_default_mac_addr,
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@ -3125,7 +3125,7 @@ txgbe_dcb_hw_configure(struct rte_eth_dev *dev,
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struct txgbe_dcb_config *dcb_config)
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{
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int ret = 0;
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uint8_t i, nb_tcs;
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uint8_t i, pfc_en, nb_tcs;
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uint16_t pbsize, rx_buffer_size;
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uint8_t config_dcb_rx = 0;
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uint8_t config_dcb_tx = 0;
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@ -3299,6 +3299,26 @@ txgbe_dcb_hw_configure(struct rte_eth_dev *dev,
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/* Configure queue statistics registers */
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txgbe_dcb_config_tc_stats_raptor(hw, dcb_config);
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/* Check if the PFC is supported */
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if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
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pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
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for (i = 0; i < nb_tcs; i++) {
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/* If the TC count is 8,
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* and the default high_water is 48,
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* the low_water is 16 as default.
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*/
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hw->fc.high_water[i] = (pbsize * 3) / 4;
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hw->fc.low_water[i] = pbsize / 4;
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/* Enable pfc for this TC */
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tc = &dcb_config->tc_config[i];
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tc->pfc = txgbe_dcb_pfc_enabled;
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}
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txgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
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if (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
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pfc_en &= 0x0F;
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ret = txgbe_dcb_config_pfc(hw, pfc_en, map);
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}
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return ret;
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}
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