net/mlx5: create clock queue for packet pacing
This patch creates the special completion queue providing reference completions to schedule packet send from other transmitting queues. Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
This commit is contained in:
Viacheslav Ovsiienko
Ferruh Yigit
parent
fc4d4f732b
commit
d133f4cdb7
@ -11,6 +11,7 @@ LIB = librte_pmd_mlx5.a
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SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5.c
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SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5_rxq.c
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SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5_txq.c
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SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5_txpp.c
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SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5_rxtx.c
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ifneq ($(filter y,$(CONFIG_RTE_ARCH_X86_64) \
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$(CONFIG_RTE_ARCH_PPC_64) \
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@ -1869,6 +1869,9 @@ mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
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{
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int dbmap_env;
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int err = 0;
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sh->numa_node = spawn->pci_dev->device.numa_node;
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pthread_mutex_init(&sh->txpp.mutex, NULL);
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/*
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* Configure environment variable "MLX5_BF_SHUT_UP"
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* before the device creation. The rdma_core library
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@ -26,6 +26,7 @@ sources = files(
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'mlx5_stats.c',
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'mlx5_trigger.c',
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'mlx5_txq.c',
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'mlx5_txpp.c',
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'mlx5_vlan.c',
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'mlx5_utils.c',
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)
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@ -767,6 +767,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
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pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
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return sh;
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error:
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pthread_mutex_destroy(&sh->txpp.mutex);
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pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
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MLX5_ASSERT(sh);
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if (sh->cnt_id_tbl) {
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@ -856,6 +857,7 @@ mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
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claim_zero(mlx5_glue->close_device(sh->ctx));
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if (sh->flow_id_pool)
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mlx5_flow_id_pool_release(sh->flow_id_pool);
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pthread_mutex_destroy(&sh->txpp.mutex);
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rte_free(sh);
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exit:
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pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
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@ -531,6 +531,44 @@ struct mlx5_flow_id_pool {
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uint32_t max_id; /**< Maximum id can be allocated from the pool. */
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};
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/* Tx pacing queue structure - for Clock and Rearm queues. */
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struct mlx5_txpp_wq {
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/* Completion Queue related data.*/
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struct mlx5_devx_obj *cq;
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struct mlx5dv_devx_umem *cq_umem;
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union {
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volatile void *cq_buf;
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volatile struct mlx5_cqe *cqes;
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};
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volatile uint32_t *cq_dbrec;
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uint32_t cq_ci:24;
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uint32_t arm_sn:2;
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/* Send Queue related data.*/
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struct mlx5_devx_obj *sq;
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struct mlx5dv_devx_umem *sq_umem;
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union {
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volatile void *sq_buf;
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volatile struct mlx5_wqe *wqes;
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};
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uint16_t sq_size; /* Number of WQEs in the queue. */
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uint16_t sq_ci; /* Next WQE to execute. */
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volatile uint32_t *sq_dbrec;
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};
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/* Tx packet pacing structure. */
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struct mlx5_dev_txpp {
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pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
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uint32_t refcnt; /* Pacing reference counter. */
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uint32_t freq; /* Timestamp frequency, Hz. */
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uint32_t tick; /* Completion tick duration in nanoseconds. */
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uint32_t test; /* Packet pacing test mode. */
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int32_t skew; /* Scheduling skew. */
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uint32_t eqn; /* Event Queue number. */
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struct rte_intr_handle intr_handle; /* Periodic interrupt. */
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struct mlx5dv_devx_event_channel *echan; /* Event Channel. */
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struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
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};
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/*
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* Shared Infiniband device context for Master/Representors
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* which belong to same IB device with multiple IB ports.
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@ -547,9 +585,12 @@ struct mlx5_dev_ctx_shared {
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char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */
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char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */
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struct mlx5_dev_attr device_attr; /* Device properties. */
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int numa_node; /* Numa node of backing physical device. */
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LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
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/**< Called by memory event callback. */
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struct mlx5_mr_share_cache share_cache;
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/* Packet pacing related structure. */
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struct mlx5_dev_txpp txpp;
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/* Shared DV/DR flow data section. */
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pthread_mutex_t dv_mutex; /* DV context mutex. */
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uint32_t dv_meta_mask; /* flow META metadata supported mask. */
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@ -622,6 +663,7 @@ struct mlx5_priv {
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unsigned int representor:1; /* Device is a port representor. */
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unsigned int master:1; /* Device is a E-Switch master. */
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unsigned int dr_shared:1; /* DV/DR data is shared. */
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unsigned int txpp_en:1; /* Tx packet pacing enabled. */
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unsigned int counter_fallback:1; /* Use counter fallback management. */
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unsigned int mtr_en:1; /* Whether support meter. */
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unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
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@ -944,4 +986,9 @@ int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
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void mlx5_os_stats_init(struct rte_eth_dev *dev);
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void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
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mlx5_dereg_mr_t *dereg_mr_cb);
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/* mlx5_txpp.c */
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int mlx5_txpp_start(struct rte_eth_dev *dev);
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void mlx5_txpp_stop(struct rte_eth_dev *dev);
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#endif /* RTE_PMD_MLX5_H_ */
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@ -171,6 +171,13 @@
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#define MLX5_TXDB_NCACHED 1
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#define MLX5_TXDB_HEURISTIC 2
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/* Tx accurate scheduling on timestamps parameters. */
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#define MLX5_TXPP_CLKQ_SIZE 1
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/* The minimal size test packet to put into one WQE, padded by HW. */
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#define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \
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sizeof(struct rte_ipv4_hdr))
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/* Size of the simple hash table for metadata register table. */
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#define MLX5_FLOW_MREG_HTABLE_SZ 4096
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#define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE"
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@ -288,25 +288,29 @@ mlx5_dev_start(struct rte_eth_dev *dev)
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return -rte_errno;
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}
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}
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ret = mlx5_txpp_start(dev);
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if (ret) {
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DRV_LOG(ERR, "port %u Tx packet pacing init failed: %s",
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dev->data->port_id, strerror(rte_errno));
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goto error;
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}
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ret = mlx5_txq_start(dev);
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if (ret) {
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DRV_LOG(ERR, "port %u Tx queue allocation failed: %s",
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dev->data->port_id, strerror(rte_errno));
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return -rte_errno;
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goto error;
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}
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ret = mlx5_rxq_start(dev);
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if (ret) {
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DRV_LOG(ERR, "port %u Rx queue allocation failed: %s",
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dev->data->port_id, strerror(rte_errno));
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mlx5_txq_stop(dev);
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return -rte_errno;
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goto error;
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}
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ret = mlx5_hairpin_bind(dev);
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if (ret) {
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DRV_LOG(ERR, "port %u hairpin binding failed: %s",
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dev->data->port_id, strerror(rte_errno));
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mlx5_txq_stop(dev);
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return -rte_errno;
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goto error;
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}
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/* Set started flag here for the following steps like control flow. */
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dev->data->dev_started = 1;
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@ -362,6 +366,7 @@ mlx5_dev_start(struct rte_eth_dev *dev)
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mlx5_traffic_disable(dev);
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mlx5_txq_stop(dev);
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mlx5_rxq_stop(dev);
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mlx5_txpp_stop(dev); /* Stop last. */
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rte_errno = ret; /* Restore rte_errno. */
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return -rte_errno;
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}
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@ -398,6 +403,7 @@ mlx5_dev_stop(struct rte_eth_dev *dev)
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priv->sh->port[priv->dev_port - 1].devx_ih_port_id = RTE_MAX_ETHPORTS;
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mlx5_txq_stop(dev);
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mlx5_rxq_stop(dev);
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mlx5_txpp_stop(dev);
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}
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/**
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449
drivers/net/mlx5/mlx5_txpp.c
Normal file
449
drivers/net/mlx5/mlx5_txpp.c
Normal file
@ -0,0 +1,449 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2020 Mellanox Technologies, Ltd
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*/
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#include <rte_ether.h>
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#include <rte_ethdev_driver.h>
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#include <rte_interrupts.h>
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#include <rte_alarm.h>
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#include <rte_malloc.h>
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#include "mlx5.h"
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#include "mlx5_rxtx.h"
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/* Destroy Event Queue Notification Channel. */
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static void
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mlx5_txpp_destroy_eqn(struct mlx5_dev_ctx_shared *sh)
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{
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if (sh->txpp.echan) {
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mlx5_glue->devx_destroy_event_channel(sh->txpp.echan);
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sh->txpp.echan = NULL;
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}
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sh->txpp.eqn = 0;
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}
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/* Create Event Queue Notification Channel. */
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static int
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mlx5_txpp_create_eqn(struct mlx5_dev_ctx_shared *sh)
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{
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uint32_t lcore;
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MLX5_ASSERT(!sh->txpp.echan);
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lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
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if (mlx5_glue->devx_query_eqn(sh->ctx, lcore, &sh->txpp.eqn)) {
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rte_errno = errno;
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DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
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sh->txpp.eqn = 0;
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return -rte_errno;
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}
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sh->txpp.echan = mlx5_glue->devx_create_event_channel(sh->ctx,
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MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
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if (!sh->txpp.echan) {
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sh->txpp.eqn = 0;
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rte_errno = errno;
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DRV_LOG(ERR, "Failed to create event channel %d.",
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rte_errno);
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return -rte_errno;
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}
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return 0;
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}
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static void
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mlx5_txpp_destroy_clock_queue(struct mlx5_dev_ctx_shared *sh)
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{
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struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
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if (wq->sq)
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claim_zero(mlx5_devx_cmd_destroy(wq->sq));
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if (wq->sq_umem)
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claim_zero(mlx5_glue->devx_umem_dereg(wq->sq_umem));
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if (wq->sq_buf)
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rte_free((void *)(uintptr_t)wq->sq_buf);
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if (wq->cq)
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claim_zero(mlx5_devx_cmd_destroy(wq->cq));
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if (wq->cq_umem)
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claim_zero(mlx5_glue->devx_umem_dereg(wq->cq_umem));
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if (wq->cq_buf)
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rte_free((void *)(uintptr_t)wq->cq_buf);
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memset(wq, 0, sizeof(*wq));
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}
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static void
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mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh)
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{
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struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
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struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes;
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struct mlx5_wqe_cseg *cs = &wqe->cseg;
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uint32_t wqe_size, opcode, i;
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uint8_t *dst;
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/* For test purposes fill the WQ with SEND inline packet. */
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if (sh->txpp.test) {
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wqe_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
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MLX5_WQE_CSEG_SIZE +
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2 * MLX5_WQE_ESEG_SIZE -
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MLX5_ESEG_MIN_INLINE_SIZE,
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MLX5_WSEG_SIZE);
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opcode = MLX5_OPCODE_SEND;
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} else {
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wqe_size = MLX5_WSEG_SIZE;
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opcode = MLX5_OPCODE_NOP;
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}
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cs->opcode = rte_cpu_to_be_32(opcode | 0); /* Index is ignored. */
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cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) |
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(wqe_size / MLX5_WSEG_SIZE));
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cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET);
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cs->misc = RTE_BE32(0);
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wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE);
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if (sh->txpp.test) {
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struct mlx5_wqe_eseg *es = &wqe->eseg;
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struct rte_ether_hdr *eth_hdr;
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struct rte_ipv4_hdr *ip_hdr;
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struct rte_udp_hdr *udp_hdr;
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/* Build the inline test packet pattern. */
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MLX5_ASSERT(wqe_size <= MLX5_WQE_SIZE_MAX);
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MLX5_ASSERT(MLX5_TXPP_TEST_PKT_SIZE >=
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(sizeof(struct rte_ether_hdr) +
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sizeof(struct rte_ipv4_hdr)));
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es->flags = 0;
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es->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
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es->swp_offs = 0;
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es->metadata = 0;
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es->swp_flags = 0;
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es->mss = 0;
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es->inline_hdr_sz = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE);
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/* Build test packet L2 header (Ethernet). */
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dst = (uint8_t *)&es->inline_data;
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eth_hdr = (struct rte_ether_hdr *)dst;
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rte_eth_random_addr(ð_hdr->d_addr.addr_bytes[0]);
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rte_eth_random_addr(ð_hdr->s_addr.addr_bytes[0]);
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eth_hdr->ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
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/* Build test packet L3 header (IP v4). */
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dst += sizeof(struct rte_ether_hdr);
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ip_hdr = (struct rte_ipv4_hdr *)dst;
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ip_hdr->version_ihl = RTE_IPV4_VHL_DEF;
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ip_hdr->type_of_service = 0;
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ip_hdr->fragment_offset = 0;
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ip_hdr->time_to_live = 64;
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ip_hdr->next_proto_id = IPPROTO_UDP;
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ip_hdr->packet_id = 0;
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ip_hdr->total_length = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
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sizeof(struct rte_ether_hdr));
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/* use RFC5735 / RFC2544 reserved network test addresses */
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ip_hdr->src_addr = RTE_BE32((198U << 24) | (18 << 16) |
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(0 << 8) | 1);
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ip_hdr->dst_addr = RTE_BE32((198U << 24) | (18 << 16) |
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(0 << 8) | 2);
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if (MLX5_TXPP_TEST_PKT_SIZE <
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(sizeof(struct rte_ether_hdr) +
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sizeof(struct rte_ipv4_hdr) +
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sizeof(struct rte_udp_hdr)))
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goto wcopy;
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/* Build test packet L4 header (UDP). */
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dst += sizeof(struct rte_ipv4_hdr);
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udp_hdr = (struct rte_udp_hdr *)dst;
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udp_hdr->src_port = RTE_BE16(9); /* RFC863 Discard. */
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udp_hdr->dst_port = RTE_BE16(9);
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udp_hdr->dgram_len = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
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sizeof(struct rte_ether_hdr) -
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sizeof(struct rte_ipv4_hdr));
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udp_hdr->dgram_cksum = 0;
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/* Fill the test packet data. */
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dst += sizeof(struct rte_udp_hdr);
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for (i = sizeof(struct rte_ether_hdr) +
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sizeof(struct rte_ipv4_hdr) +
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sizeof(struct rte_udp_hdr);
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i < MLX5_TXPP_TEST_PKT_SIZE; i++)
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*dst++ = (uint8_t)(i & 0xFF);
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}
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wcopy:
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/* Duplicate the pattern to the next WQEs. */
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dst = (uint8_t *)(uintptr_t)wq->sq_buf;
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for (i = 1; i < MLX5_TXPP_CLKQ_SIZE; i++) {
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dst += wqe_size;
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rte_memcpy(dst, (void *)(uintptr_t)wq->sq_buf, wqe_size);
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}
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}
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/* Creates the Clock Queue for packet pacing, returns zero on success. */
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static int
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mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
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{
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struct mlx5_devx_create_sq_attr sq_attr = { 0 };
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struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
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struct mlx5_devx_cq_attr cq_attr = { 0 };
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struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
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size_t page_size = sysconf(_SC_PAGESIZE);
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uint32_t umem_size, umem_dbrec;
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int ret;
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/* Allocate memory buffer for CQEs and doorbell record. */
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umem_size = sizeof(struct mlx5_cqe) * MLX5_TXPP_CLKQ_SIZE;
|
||||
umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
|
||||
umem_size += MLX5_DBR_SIZE;
|
||||
wq->cq_buf = rte_zmalloc_socket(__func__, umem_size,
|
||||
page_size, sh->numa_node);
|
||||
if (!wq->cq_buf) {
|
||||
DRV_LOG(ERR, "Failed to allocate memory for Clock Queue.");
|
||||
return -ENOMEM;
|
||||
}
|
||||
/* Register allocated buffer in user space with DevX. */
|
||||
wq->cq_umem = mlx5_glue->devx_umem_reg(sh->ctx,
|
||||
(void *)(uintptr_t)wq->cq_buf,
|
||||
umem_size,
|
||||
IBV_ACCESS_LOCAL_WRITE);
|
||||
if (!wq->cq_umem) {
|
||||
rte_errno = errno;
|
||||
DRV_LOG(ERR, "Failed to register umem for Clock Queue.");
|
||||
goto error;
|
||||
}
|
||||
/* Create completion queue object for Clock Queue. */
|
||||
cq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?
|
||||
MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;
|
||||
cq_attr.use_first_only = 1;
|
||||
cq_attr.overrun_ignore = 1;
|
||||
cq_attr.uar_page_id = sh->tx_uar->page_id;
|
||||
cq_attr.eqn = sh->txpp.eqn;
|
||||
cq_attr.q_umem_valid = 1;
|
||||
cq_attr.q_umem_offset = 0;
|
||||
cq_attr.q_umem_id = wq->cq_umem->umem_id;
|
||||
cq_attr.db_umem_valid = 1;
|
||||
cq_attr.db_umem_offset = umem_dbrec;
|
||||
cq_attr.db_umem_id = wq->cq_umem->umem_id;
|
||||
cq_attr.log_cq_size = rte_log2_u32(MLX5_TXPP_CLKQ_SIZE);
|
||||
cq_attr.log_page_size = rte_log2_u32(page_size);
|
||||
wq->cq = mlx5_devx_cmd_create_cq(sh->ctx, &cq_attr);
|
||||
if (!wq->cq) {
|
||||
rte_errno = errno;
|
||||
DRV_LOG(ERR, "Failed to create CQ for Clock Queue.");
|
||||
goto error;
|
||||
}
|
||||
wq->cq_dbrec = RTE_PTR_ADD(wq->cq_buf, umem_dbrec);
|
||||
wq->cq_ci = 0;
|
||||
/* Allocate memory buffer for Send Queue WQEs. */
|
||||
if (sh->txpp.test) {
|
||||
wq->sq_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
|
||||
MLX5_WQE_CSEG_SIZE +
|
||||
2 * MLX5_WQE_ESEG_SIZE -
|
||||
MLX5_ESEG_MIN_INLINE_SIZE,
|
||||
MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
|
||||
wq->sq_size *= MLX5_TXPP_CLKQ_SIZE;
|
||||
} else {
|
||||
wq->sq_size = MLX5_TXPP_CLKQ_SIZE;
|
||||
}
|
||||
/* There should not be WQE leftovers in the cyclic queue. */
|
||||
MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
|
||||
umem_size = MLX5_WQE_SIZE * wq->sq_size;
|
||||
umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
|
||||
umem_size += MLX5_DBR_SIZE;
|
||||
wq->sq_buf = rte_zmalloc_socket(__func__, umem_size,
|
||||
page_size, sh->numa_node);
|
||||
if (!wq->sq_buf) {
|
||||
DRV_LOG(ERR, "Failed to allocate memory for Clock Queue.");
|
||||
rte_errno = ENOMEM;
|
||||
goto error;
|
||||
}
|
||||
/* Register allocated buffer in user space with DevX. */
|
||||
wq->sq_umem = mlx5_glue->devx_umem_reg(sh->ctx,
|
||||
(void *)(uintptr_t)wq->sq_buf,
|
||||
umem_size,
|
||||
IBV_ACCESS_LOCAL_WRITE);
|
||||
if (!wq->sq_umem) {
|
||||
rte_errno = errno;
|
||||
DRV_LOG(ERR, "Failed to register umem for Clock Queue.");
|
||||
goto error;
|
||||
}
|
||||
/* Create send queue object for Clock Queue. */
|
||||
if (sh->txpp.test) {
|
||||
sq_attr.tis_lst_sz = 1;
|
||||
sq_attr.tis_num = sh->tis->id;
|
||||
sq_attr.non_wire = 0;
|
||||
sq_attr.static_sq_wq = 1;
|
||||
} else {
|
||||
sq_attr.non_wire = 1;
|
||||
sq_attr.static_sq_wq = 1;
|
||||
}
|
||||
sq_attr.state = MLX5_SQC_STATE_RST;
|
||||
sq_attr.cqn = wq->cq->id;
|
||||
sq_attr.wq_attr.cd_slave = 1;
|
||||
sq_attr.wq_attr.uar_page = sh->tx_uar->page_id;
|
||||
sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
|
||||
sq_attr.wq_attr.pd = sh->pdn;
|
||||
sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
|
||||
sq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size);
|
||||
sq_attr.wq_attr.dbr_umem_valid = 1;
|
||||
sq_attr.wq_attr.dbr_addr = umem_dbrec;
|
||||
sq_attr.wq_attr.dbr_umem_id = wq->sq_umem->umem_id;
|
||||
sq_attr.wq_attr.wq_umem_valid = 1;
|
||||
sq_attr.wq_attr.wq_umem_id = wq->sq_umem->umem_id;
|
||||
/* umem_offset must be zero for static_sq_wq queue. */
|
||||
sq_attr.wq_attr.wq_umem_offset = 0;
|
||||
wq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);
|
||||
if (!wq->sq) {
|
||||
rte_errno = errno;
|
||||
DRV_LOG(ERR, "Failed to create SQ for Clock Queue.");
|
||||
goto error;
|
||||
}
|
||||
wq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec +
|
||||
MLX5_SND_DBR * sizeof(uint32_t));
|
||||
/* Build the WQEs in the Send Queue before goto Ready state. */
|
||||
mlx5_txpp_fill_wqe_clock_queue(sh);
|
||||
/* Change queue state to ready. */
|
||||
msq_attr.sq_state = MLX5_SQC_STATE_RST;
|
||||
msq_attr.state = MLX5_SQC_STATE_RDY;
|
||||
wq->sq_ci = 0;
|
||||
ret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr);
|
||||
if (ret) {
|
||||
DRV_LOG(ERR, "Failed to set SQ ready state Clock Queue.");
|
||||
goto error;
|
||||
}
|
||||
return 0;
|
||||
error:
|
||||
ret = -rte_errno;
|
||||
mlx5_txpp_destroy_clock_queue(sh);
|
||||
rte_errno = -ret;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* The routine initializes the packet pacing infrastructure:
|
||||
* - allocates PP context
|
||||
* - Clock CQ/SQ
|
||||
* - Rearm CQ/SQ
|
||||
* - attaches rearm interrupt handler
|
||||
*
|
||||
* Returns 0 on success, negative otherwise
|
||||
*/
|
||||
static int
|
||||
mlx5_txpp_create(struct mlx5_dev_ctx_shared *sh, struct mlx5_priv *priv)
|
||||
{
|
||||
int tx_pp = priv->config.tx_pp;
|
||||
int ret;
|
||||
|
||||
/* Store the requested pacing parameters. */
|
||||
sh->txpp.tick = tx_pp >= 0 ? tx_pp : -tx_pp;
|
||||
sh->txpp.test = !!(tx_pp < 0);
|
||||
sh->txpp.skew = priv->config.tx_skew;
|
||||
sh->txpp.freq = priv->config.hca_attr.dev_freq_khz;
|
||||
ret = mlx5_txpp_create_eqn(sh);
|
||||
if (ret)
|
||||
goto exit;
|
||||
ret = mlx5_txpp_create_clock_queue(sh);
|
||||
if (ret)
|
||||
goto exit;
|
||||
exit:
|
||||
if (ret) {
|
||||
mlx5_txpp_destroy_clock_queue(sh);
|
||||
mlx5_txpp_destroy_eqn(sh);
|
||||
sh->txpp.tick = 0;
|
||||
sh->txpp.test = 0;
|
||||
sh->txpp.skew = 0;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* The routine destroys the packet pacing infrastructure:
|
||||
* - detaches rearm interrupt handler
|
||||
* - Rearm CQ/SQ
|
||||
* - Clock CQ/SQ
|
||||
* - PP context
|
||||
*/
|
||||
static void
|
||||
mlx5_txpp_destroy(struct mlx5_dev_ctx_shared *sh)
|
||||
{
|
||||
mlx5_txpp_destroy_clock_queue(sh);
|
||||
mlx5_txpp_destroy_eqn(sh);
|
||||
sh->txpp.tick = 0;
|
||||
sh->txpp.test = 0;
|
||||
sh->txpp.skew = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Creates and starts packet pacing infrastructure on specified device.
|
||||
*
|
||||
* @param dev
|
||||
* Pointer to Ethernet device structure.
|
||||
*
|
||||
* @return
|
||||
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
||||
*/
|
||||
int
|
||||
mlx5_txpp_start(struct rte_eth_dev *dev)
|
||||
{
|
||||
struct mlx5_priv *priv = dev->data->dev_private;
|
||||
struct mlx5_dev_ctx_shared *sh = priv->sh;
|
||||
int err = 0;
|
||||
int ret;
|
||||
|
||||
if (!priv->config.tx_pp) {
|
||||
/* Packet pacing is not requested for the device. */
|
||||
MLX5_ASSERT(priv->txpp_en == 0);
|
||||
return 0;
|
||||
}
|
||||
if (priv->txpp_en) {
|
||||
/* Packet pacing is already enabled for the device. */
|
||||
MLX5_ASSERT(sh->txpp.refcnt);
|
||||
return 0;
|
||||
}
|
||||
if (priv->config.tx_pp > 0) {
|
||||
ret = rte_mbuf_dynflag_lookup
|
||||
(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
}
|
||||
ret = pthread_mutex_lock(&sh->txpp.mutex);
|
||||
MLX5_ASSERT(!ret);
|
||||
RTE_SET_USED(ret);
|
||||
if (sh->txpp.refcnt) {
|
||||
priv->txpp_en = 1;
|
||||
++sh->txpp.refcnt;
|
||||
} else {
|
||||
err = mlx5_txpp_create(sh, priv);
|
||||
if (!err) {
|
||||
MLX5_ASSERT(sh->txpp.tick);
|
||||
priv->txpp_en = 1;
|
||||
sh->txpp.refcnt = 1;
|
||||
} else {
|
||||
rte_errno = -err;
|
||||
}
|
||||
}
|
||||
ret = pthread_mutex_unlock(&sh->txpp.mutex);
|
||||
MLX5_ASSERT(!ret);
|
||||
RTE_SET_USED(ret);
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* Stops and destroys packet pacing infrastructure on specified device.
|
||||
*
|
||||
* @param dev
|
||||
* Pointer to Ethernet device structure.
|
||||
*
|
||||
* @return
|
||||
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
||||
*/
|
||||
void
|
||||
mlx5_txpp_stop(struct rte_eth_dev *dev)
|
||||
{
|
||||
struct mlx5_priv *priv = dev->data->dev_private;
|
||||
struct mlx5_dev_ctx_shared *sh = priv->sh;
|
||||
int ret;
|
||||
|
||||
if (!priv->txpp_en) {
|
||||
/* Packet pacing is already disabled for the device. */
|
||||
return;
|
||||
}
|
||||
priv->txpp_en = 0;
|
||||
ret = pthread_mutex_lock(&sh->txpp.mutex);
|
||||
MLX5_ASSERT(!ret);
|
||||
RTE_SET_USED(ret);
|
||||
MLX5_ASSERT(sh->txpp.refcnt);
|
||||
if (!sh->txpp.refcnt || --sh->txpp.refcnt)
|
||||
return;
|
||||
/* No references any more, do actual destroy. */
|
||||
mlx5_txpp_destroy(sh);
|
||||
ret = pthread_mutex_unlock(&sh->txpp.mutex);
|
||||
MLX5_ASSERT(!ret);
|
||||
RTE_SET_USED(ret);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user