net/mlx5: fix inline length exceeding descriptor limit
The hardware descriptor (WQE) length field is 6 bits wide and we have the native limitation for the overall descriptor length. To improve the PCIe bandwidth the packet data can be inline into descriptor. If PMD was configured to inline large amount of data it happened there was no enough space remaining in the descriptor to specify all the packet data segments and PMD rejected problematic packets. The patch tries to adjust the inline data length conservatively and allows to avoid error occurring. Fixes:18a1c20044
("net/mlx5: implement Tx burst template") Fixes:e2259f93ef
("net/mlx5: fix Tx when inlining is impossible") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com> Reviewed-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
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@ -2078,8 +2078,24 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
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if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
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return MLX5_TXCMP_CODE_EXIT;
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/* Check for maximal WQE size. */
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if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ds))
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return MLX5_TXCMP_CODE_ERROR;
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if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ds)) {
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/* Check if we can adjust the inline length. */
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if (unlikely(txq->inlen_mode)) {
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ds = NB_SEGS(loc->mbuf) + 2 +
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(txq->inlen_mode -
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MLX5_ESEG_MIN_INLINE_SIZE +
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MLX5_WSEG_SIZE +
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MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
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if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ds))
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return MLX5_TXCMP_CODE_ERROR;
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}
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/* We have lucky opportunity to adjust. */
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inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX -
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MLX5_WSEG_SIZE * 2 -
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MLX5_WSEG_SIZE * NB_SEGS(loc->mbuf) -
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MLX5_WSEG_SIZE +
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MLX5_ESEG_MIN_INLINE_SIZE);
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}
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#ifdef MLX5_PMD_SOFT_COUNTERS
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/* Update sent data bytes/packets counters. */
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txq->stats.obytes += dlen + vlan;
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