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ixgbe/base: reset VF registers

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Reset VF registers to initial values in IXGBE base code.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
This commit is contained in:
Ouyang Changchun 2014-09-29 15:16:23 +08:00 committed by Thomas Monjalon
parent 558136b918
commit d17d0b7a24
2 changed files with 50 additions and 0 deletions
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4
lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
View File

@ -2241,6 +2241,10 @@ enum {
/* SRRCTL bit definitions */
#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* 64byte resolution (>> 6)
* + at bit 8 offset (<< 8)
* = (<< 2)
*/
#define IXGBE_SRRCTL_RDMTS_SHIFT 22
#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
#define IXGBE_SRRCTL_DROP_EN 0x10000000

46
lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c
View File

@ -89,6 +89,49 @@ s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw)
return IXGBE_SUCCESS;
}
/* ixgbe_virt_clr_reg - Set register to default (power on) state.
* @hw: pointer to hardware structure
*/
static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw)
{
int i;
u32 vfsrrctl;
u32 vfdca_rxctrl;
u32 vfdca_txctrl;
/* VRSRRCTL default values (BSIZEPACKET = 2048, BSIZEHEADER = 256) */
vfsrrctl = 0x100 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
vfsrrctl |= 0x800 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
/* DCA_RXCTRL default value */
vfdca_rxctrl = IXGBE_DCA_RXCTRL_DESC_RRO_EN |
IXGBE_DCA_RXCTRL_DATA_WRO_EN |
IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
/* DCA_TXCTRL default value */
vfdca_txctrl = IXGBE_DCA_TXCTRL_DESC_RRO_EN |
IXGBE_DCA_TXCTRL_DESC_WRO_EN |
IXGBE_DCA_TXCTRL_DATA_RRO_EN;
IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
for (i = 0; i < 7; i++) {
IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl);
IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(i), vfdca_rxctrl);
IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), vfdca_txctrl);
}
IXGBE_WRITE_FLUSH(hw);
}
/**
* ixgbe_start_hw_vf - Prepare hardware for Tx/Rx
* @hw: pointer to hardware structure
@ -161,6 +204,9 @@ s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)
if (!timeout)
return IXGBE_ERR_RESET_FAILED;
/* Reset VF registers to initial values */
ixgbe_virt_clr_reg(hw);
/* mailbox timeout can now become active */
mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT;