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net/cxgbe: add base for enabling VF ports

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Add base to enable VF ports in subsequent patches.

Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
This commit is contained in:
Kumar Sanghvi 2018-03-11 04:18:21 +05:30 committed by Ferruh Yigit
parent 179a74f7b2
commit d2adea1746
6 changed files with 544 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/net/cxgbe/base/common.h
View File

@ -210,12 +210,29 @@ struct arch_specific_params {
u16 mps_tcam_size;
};
/*
* Maximum resources provisioned for a PCI VF.
*/
struct vf_resources {
unsigned int nvi; /* N virtual interfaces */
unsigned int neq; /* N egress Qs */
unsigned int nethctrl; /* N egress ETH or CTRL Qs */
unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
unsigned int niq; /* N ingress Qs */
unsigned int tc; /* PCI-E traffic class */
unsigned int pmask; /* port access rights mask */
unsigned int nexactf; /* N exact MPS filters */
unsigned int r_caps; /* read capabilities */
unsigned int wx_caps; /* write/execute capabilities */
};
struct adapter_params {
struct sge_params sge;
struct tp_params tp;
struct vpd_params vpd;
struct pci_params pci;
struct devlog_params devlog;
struct vf_resources vfres;
enum pcie_memwin drv_memwin;
unsigned int sf_size; /* serial flash size in bytes */
@ -312,9 +329,11 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
enum dev_master master, enum dev_state *state);
int t4_fw_bye(struct adapter *adap, unsigned int mbox);
int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
int t4vf_fw_reset(struct adapter *adap);
int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
int t4_fl_pkt_align(struct adapter *adap);
int t4vf_get_vfres(struct adapter *adap);
int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
unsigned int cache_line_size,
enum chip_type chip_compat);
@ -324,6 +343,12 @@ int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
unsigned int vf, unsigned int nparams, const u32 *params,
u32 *val);
int t4vf_query_params(struct adapter *adap, unsigned int nparams,
const u32 *params, u32 *vals);
int t4vf_get_dev_params(struct adapter *adap);
int t4vf_get_vpd_params(struct adapter *adap);
int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
const u32 *params, const u32 *vals);
int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
unsigned int pf, unsigned int vf,
unsigned int nparams, const u32 *params,
@ -440,13 +465,17 @@ void t4_get_port_stats_offset(struct adapter *adap, int idx,
struct port_stats *stats,
struct port_stats *offset);
void t4_clr_port_stats(struct adapter *adap, int idx);
void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
fw_port_cap32_t acaps);
void t4_reset_link_config(struct adapter *adap, int idx);
int t4_get_version_info(struct adapter *adapter);
void t4_dump_version_info(struct adapter *adapter);
int t4_get_flash_params(struct adapter *adapter);
int t4_get_chip_type(struct adapter *adap, int ver);
int t4_prep_adapter(struct adapter *adapter);
int t4vf_prep_adapter(struct adapter *adapter);
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
int t4vf_port_init(struct adapter *adap);
int t4_init_rss_mode(struct adapter *adap, int mbox);
int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
int start, int n, const u16 *rspq, unsigned int nrspq);
@ -469,8 +498,10 @@ int t4_init_tp_params(struct adapter *adap);
int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
unsigned int t4_get_regs_len(struct adapter *adap);
unsigned int t4vf_get_pf_from_vf(struct adapter *adap);
void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
int t4_seeprom_wp(struct adapter *adapter, int enable);
fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
#endif /* __CHELSIO_COMMON_H */

9
drivers/net/cxgbe/base/t4_hw.c
View File

@ -55,9 +55,6 @@
#include "t4_regs_values.h"
#include "t4fw_interface.h"
static void init_link_config(struct link_config *lc, unsigned int pcaps,
unsigned int acaps);
/**
* t4_read_mtu_tbl - returns the values in the HW path MTU table
* @adap: the adapter
@ -2804,7 +2801,7 @@ void t4_dump_version_info(struct adapter *adapter)
*
* Returns the equivalent 32-bit Port Capabilities value.
*/
static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
{
fw_port_cap32_t caps32 = 0;
@ -4585,8 +4582,8 @@ void t4_reset_link_config(struct adapter *adap, int idx)
* Initializes the SW state maintained for each link, including the link's
* capabilities and default speed/flow-control/autonegotiation settings.
*/
static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
fw_port_cap32_t acaps)
void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
fw_port_cap32_t acaps)
{
lc->pcaps = pcaps;
lc->requested_speed = 0;

2
drivers/net/cxgbe/base/t4_regs.h
View File

@ -852,6 +852,7 @@
#define F_PFCIM V_PFCIM(1U)
#define A_PL_WHOAMI 0x19400
#define A_PL_VF_WHOAMI 0x0
#define A_PL_RST 0x19428
@ -866,6 +867,7 @@
#define F_PIORSTMODE V_PIORSTMODE(1U)
#define A_PL_REV 0x1943c
#define A_PL_VF_REV 0x4
#define S_REV 0
#define M_REV 0xfU

73
drivers/net/cxgbe/base/t4fw_interface.h
View File

@ -178,6 +178,7 @@ enum fw_cmd_opcodes {
FW_INITIALIZE_CMD = 0x06,
FW_CAPS_CONFIG_CMD = 0x07,
FW_PARAMS_CMD = 0x08,
FW_PFVF_CMD = 0x09,
FW_IQ_CMD = 0x10,
FW_EQ_ETH_CMD = 0x12,
FW_VI_CMD = 0x14,
@ -190,6 +191,10 @@ enum fw_cmd_opcodes {
FW_DEBUG_CMD = 0x81,
};
enum fw_cmd_cap {
FW_CMD_CAP_PORT = 0x04,
};
/*
* Generic command header flit0
*/
@ -484,6 +489,8 @@ enum fw_params_mnem {
enum fw_params_param_dev {
FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */
FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */
FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
};
@ -533,6 +540,10 @@ enum fw_params_param_dmaq {
#define G_FW_PARAMS_PARAM_YZ(x) \
(((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
#define S_FW_PARAMS_PARAM_XYZ 0
#define M_FW_PARAMS_PARAM_XYZ 0xffffff
#define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
struct fw_params_cmd {
__be32 op_to_vfn;
__be32 retval_len16;
@ -554,6 +565,68 @@ struct fw_params_cmd {
#define G_FW_PARAMS_CMD_VFN(x) \
(((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
struct fw_pfvf_cmd {
__be32 op_to_vfn;
__be32 retval_len16;
__be32 niqflint_niq;
__be32 type_to_neq;
__be32 tc_to_nexactf;
__be32 r_caps_to_nethctrl;
__be16 nricq;
__be16 nriqp;
__be32 r4;
};
#define S_FW_PFVF_CMD_NIQFLINT 20
#define M_FW_PFVF_CMD_NIQFLINT 0xfff
#define G_FW_PFVF_CMD_NIQFLINT(x) \
(((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
#define S_FW_PFVF_CMD_NIQ 0
#define M_FW_PFVF_CMD_NIQ 0xfffff
#define G_FW_PFVF_CMD_NIQ(x) \
(((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
#define S_FW_PFVF_CMD_PMASK 20
#define M_FW_PFVF_CMD_PMASK 0xf
#define G_FW_PFVF_CMD_PMASK(x) \
(((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
#define S_FW_PFVF_CMD_NEQ 0
#define M_FW_PFVF_CMD_NEQ 0xfffff
#define G_FW_PFVF_CMD_NEQ(x) \
(((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
#define S_FW_PFVF_CMD_TC 24
#define M_FW_PFVF_CMD_TC 0xff
#define G_FW_PFVF_CMD_TC(x) \
(((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
#define S_FW_PFVF_CMD_NVI 16
#define M_FW_PFVF_CMD_NVI 0xff
#define G_FW_PFVF_CMD_NVI(x) \
(((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
#define S_FW_PFVF_CMD_NEXACTF 0
#define M_FW_PFVF_CMD_NEXACTF 0xffff
#define G_FW_PFVF_CMD_NEXACTF(x) \
(((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
#define S_FW_PFVF_CMD_R_CAPS 24
#define M_FW_PFVF_CMD_R_CAPS 0xff
#define G_FW_PFVF_CMD_R_CAPS(x) \
(((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
#define S_FW_PFVF_CMD_WX_CAPS 16
#define M_FW_PFVF_CMD_WX_CAPS 0xff
#define G_FW_PFVF_CMD_WX_CAPS(x) \
(((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
#define S_FW_PFVF_CMD_NETHCTRL 0
#define M_FW_PFVF_CMD_NETHCTRL 0xffff
#define G_FW_PFVF_CMD_NETHCTRL(x) \
(((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
/*
* ingress queue type; the first 1K ingress queues can have associated 0,
* 1 or 2 free lists and an interrupt, all other ingress queues lack these

434
drivers/net/cxgbe/base/t4vf_hw.c
View File

@ -9,6 +9,34 @@
#include "common.h"
#include "t4_regs.h"
/**
* t4vf_wait_dev_ready - wait till to reads of registers work
*
* Wait for the device to become ready (signified by our "who am I" register
* returning a value other than all 1's). Return an error if it doesn't
* become ready ...
*/
static int t4vf_wait_dev_ready(struct adapter *adapter)
{
const u32 whoami = T4VF_PL_BASE_ADDR + A_PL_VF_WHOAMI;
const u32 notready1 = 0xffffffff;
const u32 notready2 = 0xeeeeeeee;
u32 val;
val = t4_read_reg(adapter, whoami);
if (val != notready1 && val != notready2)
return 0;
msleep(500);
val = t4_read_reg(adapter, whoami);
if (val != notready1 && val != notready2)
return 0;
dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
val);
return -EIO;
}
/*
* Get the reply to a mailbox command and store it in @rpl in big-endian order.
*/
@ -222,3 +250,409 @@ int t4vf_wr_mbox_core(struct adapter *adapter,
ret = -ETIMEDOUT;
return ret;
}
/**
* t4vf_fw_reset - issue a reset to FW
* @adapter: the adapter
*
* Issues a reset command to FW. For a Physical Function this would
* result in the Firmware resetting all of its state. For a Virtual
* Function this just resets the state associated with the VF.
*/
int t4vf_fw_reset(struct adapter *adapter)
{
struct fw_reset_cmd cmd;
memset(&cmd, 0, sizeof(cmd));
cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RESET_CMD) |
F_FW_CMD_WRITE);
cmd.retval_len16 = cpu_to_be32(V_FW_CMD_LEN16(FW_LEN16(cmd)));
return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
}
/**
* t4vf_prep_adapter - prepare SW and HW for operation
* @adapter: the adapter
*
* Initialize adapter SW state for the various HW modules, set initial
* values for some adapter tunables, take PHYs out of reset, and
* initialize the MDIO interface.
*/
int t4vf_prep_adapter(struct adapter *adapter)
{
u32 pl_vf_rev;
int ret, ver;
ret = t4vf_wait_dev_ready(adapter);
if (ret < 0)
return ret;
/*
* Default port and clock for debugging in case we can't reach
* firmware.
*/
adapter->params.nports = 1;
adapter->params.vfres.pmask = 1;
adapter->params.vpd.cclk = 50000;
pl_vf_rev = G_REV(t4_read_reg(adapter, A_PL_VF_REV));
adapter->params.pci.device_id = adapter->pdev->id.device_id;
adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
/*
* WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
* ADAPTER (VERSION << 4 | REVISION)
*/
ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
adapter->params.chip = 0;
switch (ver) {
case CHELSIO_T5:
adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5,
pl_vf_rev);
adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
adapter->params.arch.mps_tcam_size =
NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
break;
case CHELSIO_T6:
adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6,
pl_vf_rev);
adapter->params.arch.sge_fl_db = 0;
adapter->params.arch.mps_tcam_size =
NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
break;
default:
dev_err(adapter, "%s: Device %d is not supported\n",
__func__, adapter->params.pci.device_id);
return -EINVAL;
}
return 0;
}
/**
* t4vf_query_params - query FW or device parameters
* @adapter: the adapter
* @nparams: the number of parameters
* @params: the parameter names
* @vals: the parameter values
*
* Reads the values of firmware or device parameters. Up to 7 parameters
* can be queried at once.
*/
int t4vf_query_params(struct adapter *adapter, unsigned int nparams,
const u32 *params, u32 *vals)
{
struct fw_params_cmd cmd, rpl;
struct fw_params_param *p;
unsigned int i;
size_t len16;
int ret;
if (nparams > 7)
return -EINVAL;
memset(&cmd, 0, sizeof(cmd));
cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
F_FW_CMD_REQUEST |
F_FW_CMD_READ);
len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
param[nparams]), 16);
cmd.retval_len16 = cpu_to_be32(V_FW_CMD_LEN16(len16));
for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++)
p->mnem = cpu_to_be32(*params++);
ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
if (ret == 0)
for (i = 0, p = &rpl.param[0]; i < nparams; i++, p++)
*vals++ = be32_to_cpu(p->val);
return ret;
}
/**
* t4vf_get_vpd_params - retrieve device VPD paremeters
* @adapter: the adapter
*
* Retrives various device Vital Product Data parameters. The parameters
* are stored in @adapter->params.vpd.
*/
int t4vf_get_vpd_params(struct adapter *adapter)
{
struct vpd_params *vpd_params = &adapter->params.vpd;
u32 params[7], vals[7];
int v;
params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
v = t4vf_query_params(adapter, 1, params, vals);
if (v != FW_SUCCESS)
return v;
vpd_params->cclk = vals[0];
dev_debug(adapter, "%s: vpd_params->cclk = %u\n",
__func__, vpd_params->cclk);
return 0;
}
/**
* t4vf_get_dev_params - retrieve device paremeters
* @adapter: the adapter
*
* Retrives fw and tp version.
*/
int t4vf_get_dev_params(struct adapter *adapter)
{
u32 params[7], vals[7];
int v;
params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWREV));
params[1] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPREV));
v = t4vf_query_params(adapter, 2, params, vals);
if (v != FW_SUCCESS)
return v;
adapter->params.fw_vers = vals[0];
adapter->params.tp_vers = vals[1];
dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
return 0;
}
/**
* t4vf_set_params - sets FW or device parameters
* @adapter: the adapter
* @nparams: the number of parameters
* @params: the parameter names
* @vals: the parameter values
*
* Sets the values of firmware or device parameters. Up to 7 parameters
* can be specified at once.
*/
int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
const u32 *params, const u32 *vals)
{
struct fw_params_param *p;
struct fw_params_cmd cmd;
unsigned int i;
size_t len16;
if (nparams > 7)
return -EINVAL;
memset(&cmd, 0, sizeof(cmd));
cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
F_FW_CMD_REQUEST |
F_FW_CMD_WRITE);
len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
param[nparams]), 16);
cmd.retval_len16 = cpu_to_be32(V_FW_CMD_LEN16(len16));
for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++) {
p->mnem = cpu_to_be32(*params++);
p->val = cpu_to_be32(*vals++);
}
return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
}
unsigned int t4vf_get_pf_from_vf(struct adapter *adapter)
{
u32 whoami;
whoami = t4_read_reg(adapter, T4VF_PL_BASE_ADDR + A_PL_VF_WHOAMI);
return (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami));
}
/**
* t4vf_get_vfres - retrieve VF resource limits
* @adapter: the adapter
*
* Retrieves configured resource limits and capabilities for a virtual
* function. The results are stored in @adapter->vfres.
*/
int t4vf_get_vfres(struct adapter *adapter)
{
struct vf_resources *vfres = &adapter->params.vfres;
struct fw_pfvf_cmd cmd, rpl;
u32 word;
int v;
/*
* Execute PFVF Read command to get VF resource limits; bail out early
* with error on command failure.
*/
memset(&cmd, 0, sizeof(cmd));
cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) |
F_FW_CMD_REQUEST |
F_FW_CMD_READ);
cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
if (v != FW_SUCCESS)
return v;
/*
* Extract VF resource limits and return success.
*/
word = be32_to_cpu(rpl.niqflint_niq);
vfres->niqflint = G_FW_PFVF_CMD_NIQFLINT(word);
vfres->niq = G_FW_PFVF_CMD_NIQ(word);
word = be32_to_cpu(rpl.type_to_neq);
vfres->neq = G_FW_PFVF_CMD_NEQ(word);
vfres->pmask = G_FW_PFVF_CMD_PMASK(word);
word = be32_to_cpu(rpl.tc_to_nexactf);
vfres->tc = G_FW_PFVF_CMD_TC(word);
vfres->nvi = G_FW_PFVF_CMD_NVI(word);
vfres->nexactf = G_FW_PFVF_CMD_NEXACTF(word);
word = be32_to_cpu(rpl.r_caps_to_nethctrl);
vfres->r_caps = G_FW_PFVF_CMD_R_CAPS(word);
vfres->wx_caps = G_FW_PFVF_CMD_WX_CAPS(word);
vfres->nethctrl = G_FW_PFVF_CMD_NETHCTRL(word);
return 0;
}
static int t4vf_alloc_vi(struct adapter *adapter, int port_id)
{
struct fw_vi_cmd cmd, rpl;
int v;
/*
* Execute a VI command to allocate Virtual Interface and return its
* VIID.
*/
memset(&cmd, 0, sizeof(cmd));
cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
F_FW_CMD_REQUEST |
F_FW_CMD_WRITE |
F_FW_CMD_EXEC);
cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
F_FW_VI_CMD_ALLOC);
cmd.portid_pkd = V_FW_VI_CMD_PORTID(port_id);
v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
if (v != FW_SUCCESS)
return v;
return G_FW_VI_CMD_VIID(be16_to_cpu(rpl.type_to_viid));
}
int t4vf_port_init(struct adapter *adapter)
{
unsigned int fw_caps = adapter->params.fw_caps_support;
struct fw_port_cmd port_cmd, port_rpl;
struct fw_vi_cmd vi_cmd, vi_rpl;
fw_port_cap32_t pcaps, acaps;
enum fw_port_type port_type;
int mdio_addr;
int ret, i;
for_each_port(adapter, i) {
struct port_info *p = adap2pinfo(adapter, i);
/*
* If we haven't yet determined if we're talking to Firmware
* which knows the new 32-bit Port Caps, it's time to find
* out now. This will also tell new Firmware to send us Port
* Status Updates using the new 32-bit Port Capabilities
* version of the Port Information message.
*/
if (fw_caps == FW_CAPS_UNKNOWN) {
u32 param, val;
param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) |
V_FW_PARAMS_PARAM_X
(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
val = 1;
ret = t4vf_set_params(adapter, 1, &param, &val);
fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
adapter->params.fw_caps_support = fw_caps;
}
ret = t4vf_alloc_vi(adapter, p->port_id);
if (ret < 0) {
dev_err(&pdev->dev, "cannot allocate VI for port %d:"
" err=%d\n", p->port_id, ret);
return ret;
}
p->viid = ret;
/*
* Execute a VI Read command to get our Virtual Interface
* information like MAC address, etc.
*/
memset(&vi_cmd, 0, sizeof(vi_cmd));
vi_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
F_FW_CMD_REQUEST |
F_FW_CMD_READ);
vi_cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(vi_cmd));
vi_cmd.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(p->viid));
ret = t4vf_wr_mbox(adapter, &vi_cmd, sizeof(vi_cmd), &vi_rpl);
if (ret != FW_SUCCESS)
return ret;
p->rss_size = G_FW_VI_CMD_RSSSIZE
(be16_to_cpu(vi_rpl.norss_rsssize));
t4_os_set_hw_addr(adapter, i, vi_rpl.mac);
/*
* If we don't have read access to our port information, we're
* done now. Else, execute a PORT Read command to get it ...
*/
if (!(adapter->params.vfres.r_caps & FW_CMD_CAP_PORT))
return 0;
memset(&port_cmd, 0, sizeof(port_cmd));
port_cmd.op_to_portid = cpu_to_be32
(V_FW_CMD_OP(FW_PORT_CMD) | F_FW_CMD_REQUEST |
F_FW_CMD_READ |
V_FW_PORT_CMD_PORTID(p->port_id));
port_cmd.action_to_len16 = cpu_to_be32
(V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16 ?
FW_PORT_ACTION_GET_PORT_INFO :
FW_PORT_ACTION_GET_PORT_INFO32) |
FW_LEN16(port_cmd));
ret = t4vf_wr_mbox(adapter, &port_cmd, sizeof(port_cmd),
&port_rpl);
if (ret != FW_SUCCESS)
return ret;
/*
* Extract the various fields from the Port Information message.
*/
if (fw_caps == FW_CAPS16) {
u32 lstatus = be32_to_cpu
(port_rpl.u.info.lstatus_to_modtype);
port_type = G_FW_PORT_CMD_PTYPE(lstatus);
mdio_addr = ((lstatus & F_FW_PORT_CMD_MDIOCAP) ?
(int)G_FW_PORT_CMD_MDIOADDR(lstatus) :
-1);
pcaps = fwcaps16_to_caps32
(be16_to_cpu(port_rpl.u.info.pcap));
acaps = fwcaps16_to_caps32
(be16_to_cpu(port_rpl.u.info.acap));
} else {
u32 lstatus32 = be32_to_cpu
(port_rpl.u.info32.lstatus32_to_cbllen32);
port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
mdio_addr = ((lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ?
(int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) :
-1);
pcaps = be32_to_cpu(port_rpl.u.info32.pcaps32);
acaps = be32_to_cpu(port_rpl.u.info32.acaps32);
}
p->port_type = port_type;
p->mdio_addr = mdio_addr;
p->mod_type = FW_PORT_MOD_TYPE_NA;
init_link_config(&p->link_cfg, pcaps, acaps);
}
return 0;
}

1
drivers/net/cxgbe/base/t4vf_hw.h
View File

@ -6,6 +6,7 @@
#ifndef __T4VF_HW_H
#define __T4VF_HW_H
#define T4VF_PL_BASE_ADDR 0x0200
#define T4VF_CIM_BASE_ADDR 0x0300
#define T4VF_MBDATA_BASE_ADDR 0x0240
#define T6VF_MBDATA_BASE_ADDR 0x0280