ixgbe/base: support X550
Add new file to support controller X550, therefore update the Makefile and README file. It also updates the API functions, DCB related functions, mailbox related functions, etc to support X550. In addition, some new macros used by X550 are added. Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com> [Thomas: merge dependent patches]
This commit is contained in:
Ouyang Changchun
Thomas Monjalon
parent
9fe892eb08
commit
d2e72774e5
@ -64,6 +64,7 @@ CFLAGS_BASE_DRIVER += -Wno-strict-aliasing -Wno-format-extra-args
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ifeq ($(shell test $(GCC_MAJOR_VERSION) -ge 4 -a $(GCC_MINOR_VERSION) -ge 6 && echo 1), 1)
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CFLAGS_ixgbe_common.o += -Wno-unused-but-set-variable
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CFLAGS_ixgbe_x550.o += -Wno-unused-but-set-variable -Wno-maybe-uninitialized
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endif
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endif
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@ -83,6 +84,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_common.c
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SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82598.c
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SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82599.c
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SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_x540.c
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SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_x550.c
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SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_phy.c
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SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_api.c
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SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_vf.c
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@ -34,7 +34,7 @@ Intel® IXGBE driver
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===================
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This directory contains source code of FreeBSD ixgbe driver of version
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cid-10g-shared-code.2014.03.13 released by LAD. The sub-directory of lad/
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cid-10g-shared-code.2014.09.04 released by LAD. The sub-directory of lad/
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contains the original source package.
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This driver is valid for the product(s) listed below
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@ -50,6 +50,7 @@ This driver is valid for the product(s) listed below
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* Intel® Ethernet Controller X540-AT2
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* Intel® Ethernet Server Adapter X520 Series
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* Intel® Ethernet Server Adapter X520-T2
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* Intel® Ethernet Controller X550-BT2
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Updating driver
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===============
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@ -1918,6 +1918,15 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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/* write both the same so that UDP and TCP use the same mask */
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IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
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IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
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/* also use it for SCTP */
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switch (hw->mac.type) {
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
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break;
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default:
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break;
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}
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/* store source and destination IP masks (big-endian) */
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IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
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@ -81,8 +81,16 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
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case ixgbe_mac_X540:
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status = ixgbe_init_ops_X540(hw);
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break;
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case ixgbe_mac_X550:
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status = ixgbe_init_ops_X550(hw);
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break;
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case ixgbe_mac_X550EM_x:
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status = ixgbe_init_ops_X550EM(hw);
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break;
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case ixgbe_mac_82599_vf:
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case ixgbe_mac_X540_vf:
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case ixgbe_mac_X550_vf:
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case ixgbe_mac_X550EM_x_vf:
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status = ixgbe_init_ops_vf(hw);
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break;
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default:
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@ -157,6 +165,23 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
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case IXGBE_DEV_ID_X540T1:
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hw->mac.type = ixgbe_mac_X540;
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break;
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case IXGBE_DEV_ID_X550T:
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hw->mac.type = ixgbe_mac_X550;
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break;
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case IXGBE_DEV_ID_X550EM_X:
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case IXGBE_DEV_ID_X550EM_X_KX4:
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case IXGBE_DEV_ID_X550EM_X_KR:
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case IXGBE_DEV_ID_X550EM_X_SFP:
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hw->mac.type = ixgbe_mac_X550EM_x;
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break;
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case IXGBE_DEV_ID_X550_VF:
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case IXGBE_DEV_ID_X550_VF_HV:
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hw->mac.type = ixgbe_mac_X550_vf;
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break;
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case IXGBE_DEV_ID_X550EM_X_VF:
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case IXGBE_DEV_ID_X550EM_X_VF_HV:
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hw->mac.type = ixgbe_mac_X550EM_x_vf;
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break;
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default:
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ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
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ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
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@ -44,6 +44,8 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw);
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s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
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@ -184,6 +184,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
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case IXGBE_DEV_ID_82599_T3_LOM:
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case IXGBE_DEV_ID_X540T:
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case IXGBE_DEV_ID_X540T1:
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case IXGBE_DEV_ID_X550T:
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supported = true;
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break;
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default:
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@ -563,7 +564,7 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
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}
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}
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if (hw->mac.type == ixgbe_mac_X540) {
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if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
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if (hw->phy.id == 0)
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ixgbe_identify_phy(hw);
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hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
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@ -3567,6 +3568,8 @@ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
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max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
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break;
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@ -4080,8 +4083,13 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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}
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if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
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IXGBE_LINKS_SPEED_10G_82599)
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IXGBE_LINKS_SPEED_10G_82599) {
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*speed = IXGBE_LINK_SPEED_10GB_FULL;
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if (hw->mac.type > ixgbe_mac_X550) {
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if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
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*speed = IXGBE_LINK_SPEED_2_5GB_FULL;
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}
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}
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else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
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IXGBE_LINKS_SPEED_1G_82599)
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*speed = IXGBE_LINK_SPEED_1GB_FULL;
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@ -394,6 +394,8 @@ s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
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break;
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default:
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@ -420,6 +422,8 @@ s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
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break;
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default:
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@ -457,6 +461,8 @@ s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,
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tsa, map);
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break;
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@ -494,6 +500,8 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
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bwgid, tsa);
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break;
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@ -533,6 +541,8 @@ s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
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bwgid, tsa,
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map);
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@ -566,6 +576,8 @@ s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
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break;
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default:
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@ -590,6 +602,8 @@ s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);
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break;
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default:
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@ -630,6 +644,8 @@ s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ixgbe_dcb_config_82599(hw, dcb_config);
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ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,
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refill, max, bwgid,
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@ -660,6 +676,8 @@ s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
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break;
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default:
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@ -681,6 +699,8 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
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tsa, map);
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ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
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@ -615,6 +615,8 @@ STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)
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case ixgbe_mac_82599EB:
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vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));
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break;
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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case ixgbe_mac_X540:
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vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));
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break;
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@ -761,6 +763,8 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)
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struct ixgbe_mbx_info *mbx = &hw->mbx;
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if (hw->mac.type != ixgbe_mac_82599EB &&
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hw->mac.type != ixgbe_mac_X550 &&
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hw->mac.type != ixgbe_mac_X550EM_x &&
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hw->mac.type != ixgbe_mac_X540)
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return;
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@ -97,6 +97,8 @@ enum {
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#define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i)
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#define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i)
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#define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)
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#define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i)
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#define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i)
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typedef uint8_t u8;
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typedef int8_t s8;
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@ -46,7 +46,7 @@ STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
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STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
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STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
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STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
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STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
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STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
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STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *sff8472_data);
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@ -428,6 +428,7 @@ enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
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case TN1010_PHY_ID:
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phy_type = ixgbe_phy_tn;
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break;
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case X550_PHY_ID:
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case X540_PHY_ID:
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phy_type = ixgbe_phy_aq;
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break;
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@ -2033,7 +2034,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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**/
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STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
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{
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
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DEBUGFUNC("ixgbe_i2c_start");
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@ -2064,7 +2065,7 @@ STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
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**/
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STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
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{
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
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DEBUGFUNC("ixgbe_i2c_stop");
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@ -2128,9 +2129,9 @@ STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
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}
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/* Release SDA line (set high) */
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i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
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i2cctl |= IXGBE_I2C_DATA_OUT;
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IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
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i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
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i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
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IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
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IXGBE_WRITE_FLUSH(hw);
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return status;
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@ -2146,7 +2147,7 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
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{
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s32 status = IXGBE_SUCCESS;
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u32 i = 0;
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
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u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
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u32 timeout = 10;
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bool ack = 1;
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@ -2161,17 +2162,16 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
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/* Poll for ACK. Note that ACK in I2C spec is
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* transition from 1 to 0 */
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for (i = 0; i < timeout; i++) {
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i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
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ack = ixgbe_get_i2c_data(&i2cctl);
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i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
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ack = ixgbe_get_i2c_data(hw, &i2cctl);
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usec_delay(1);
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if (!ack)
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break;
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}
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if (ack == 1) {
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ERROR_REPORT1(IXGBE_ERROR_POLLING,
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"I2C ack was not received.\n");
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if (ack) {
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DEBUGOUT("I2C ack was not received.\n");
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status = IXGBE_ERR_I2C;
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}
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@ -2192,7 +2192,7 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
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**/
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STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
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{
|
||||
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
|
||||
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
|
||||
|
||||
DEBUGFUNC("ixgbe_clock_in_i2c_bit");
|
||||
|
||||
@ -2201,8 +2201,8 @@ STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
|
||||
/* Minimum high period of clock is 4us */
|
||||
usec_delay(IXGBE_I2C_T_HIGH);
|
||||
|
||||
i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
|
||||
*data = ixgbe_get_i2c_data(&i2cctl);
|
||||
i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
|
||||
*data = ixgbe_get_i2c_data(hw, &i2cctl);
|
||||
|
||||
ixgbe_lower_i2c_clk(hw, &i2cctl);
|
||||
|
||||
@ -2222,7 +2222,7 @@ STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
|
||||
STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
|
||||
{
|
||||
s32 status;
|
||||
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
|
||||
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
|
||||
|
||||
DEBUGFUNC("ixgbe_clock_out_i2c_bit");
|
||||
|
||||
@ -2264,15 +2264,15 @@ STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
|
||||
DEBUGFUNC("ixgbe_raise_i2c_clk");
|
||||
|
||||
for (i = 0; i < timeout; i++) {
|
||||
*i2cctl |= IXGBE_I2C_CLK_OUT;
|
||||
*i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
/* SCL rise time (1000ns) */
|
||||
usec_delay(IXGBE_I2C_T_RISE);
|
||||
|
||||
i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
|
||||
if (i2cctl_r & IXGBE_I2C_CLK_IN)
|
||||
i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
|
||||
if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -2289,9 +2289,9 @@ STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
|
||||
|
||||
DEBUGFUNC("ixgbe_lower_i2c_clk");
|
||||
|
||||
*i2cctl &= ~IXGBE_I2C_CLK_OUT;
|
||||
*i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
|
||||
/* SCL fall time (300ns) */
|
||||
@ -2313,19 +2313,19 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
|
||||
DEBUGFUNC("ixgbe_set_i2c_data");
|
||||
|
||||
if (data)
|
||||
*i2cctl |= IXGBE_I2C_DATA_OUT;
|
||||
*i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
|
||||
else
|
||||
*i2cctl &= ~IXGBE_I2C_DATA_OUT;
|
||||
*i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
|
||||
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
|
||||
usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
|
||||
|
||||
/* Verify data was set correctly */
|
||||
*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
|
||||
if (data != ixgbe_get_i2c_data(i2cctl)) {
|
||||
*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
|
||||
if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
|
||||
status = IXGBE_ERR_I2C;
|
||||
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
|
||||
"Error - I2C data was not set to %X.\n",
|
||||
@ -2342,13 +2342,14 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
|
||||
*
|
||||
* Returns the I2C data bit value
|
||||
**/
|
||||
STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
|
||||
STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
|
||||
{
|
||||
bool data;
|
||||
UNREFERENCED_1PARAMETER(hw);
|
||||
|
||||
DEBUGFUNC("ixgbe_get_i2c_data");
|
||||
|
||||
if (*i2cctl & IXGBE_I2C_DATA_IN)
|
||||
if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
|
||||
data = 1;
|
||||
else
|
||||
data = 0;
|
||||
@ -2365,7 +2366,7 @@ STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
|
||||
**/
|
||||
void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
|
||||
{
|
||||
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
|
||||
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
|
||||
u32 i;
|
||||
|
||||
DEBUGFUNC("ixgbe_i2c_bus_clear");
|
||||
|
||||
@ -82,6 +82,11 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
|
||||
#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
|
||||
|
||||
#define IXGBE_CS4227 0x9E /* CS4227 address */
|
||||
#define IXGBE_CS4227_SPARE24_LSB 0x12B0 /* Reg to program EDC */
|
||||
#define IXGBE_CS4227_EDC_MODE_CX1 0x0002
|
||||
#define IXGBE_CS4227_EDC_MODE_SR 0x0004
|
||||
|
||||
/* Flow control defines */
|
||||
#define IXGBE_TAF_SYM_PAUSE 0x400
|
||||
#define IXGBE_TAF_ASM_PAUSE 0x800
|
||||
|
||||
@ -126,6 +126,15 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define IXGBE_DEV_ID_X540_VF 0x1515
|
||||
#define IXGBE_DEV_ID_X540_VF_HV 0x1530
|
||||
#define IXGBE_DEV_ID_X540T1 0x1560
|
||||
#define IXGBE_DEV_ID_X550EM_X 0x15A7
|
||||
#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
|
||||
#define IXGBE_DEV_ID_X550T 0x1563
|
||||
#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
|
||||
#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
|
||||
#define IXGBE_DEV_ID_X550_VF_HV 0x1564
|
||||
#define IXGBE_DEV_ID_X550_VF 0x1565
|
||||
#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
|
||||
#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
|
||||
|
||||
/* General Registers */
|
||||
#define IXGBE_CTRL 0x00000
|
||||
@ -133,7 +142,10 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define IXGBE_CTRL_EXT 0x00018
|
||||
#define IXGBE_ESDP 0x00020
|
||||
#define IXGBE_EODSDP 0x00028
|
||||
#define IXGBE_I2CCTL 0x00028
|
||||
#define IXGBE_I2CCTL_82599 0x00028
|
||||
#define IXGBE_I2CCTL_X550 0x15F5C
|
||||
#define IXGBE_I2CCTL_BY_MAC(_hw) ((((_hw)->mac.type >= ixgbe_mac_X550) ? \
|
||||
IXGBE_I2CCTL_X550 : IXGBE_I2CCTL_82599))
|
||||
#define IXGBE_PHY_GPIO 0x00028
|
||||
#define IXGBE_MAC_GPIO 0x00030
|
||||
#define IXGBE_PHYINT_STATUS0 0x00100
|
||||
@ -168,10 +180,14 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define IXGBE_VPDDIAG1 0x10208
|
||||
|
||||
/* I2CCTL Bit Masks */
|
||||
#define IXGBE_I2C_CLK_IN 0x00000001
|
||||
#define IXGBE_I2C_CLK_OUT 0x00000002
|
||||
#define IXGBE_I2C_DATA_IN 0x00000004
|
||||
#define IXGBE_I2C_DATA_OUT 0x00000008
|
||||
#define IXGBE_I2C_CLK_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
|
||||
0x00004000 : 0x00000001)
|
||||
#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
|
||||
0x00000200 : 0x00000002)
|
||||
#define IXGBE_I2C_DATA_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
|
||||
0x00001000 : 0x00000004)
|
||||
#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
|
||||
0x00000400 : 0x00000008)
|
||||
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
|
||||
|
||||
#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
|
||||
@ -326,6 +342,8 @@ struct ixgbe_thermal_sensor_data {
|
||||
#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
|
||||
#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
|
||||
#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
|
||||
#define IXGBE_PFFLPL 0x050B0
|
||||
#define IXGBE_PFFLPH 0x050B4
|
||||
#define IXGBE_VT_CTL 0x051B0
|
||||
#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */
|
||||
/* 64 Mailboxes, 16 DW each */
|
||||
@ -342,6 +360,12 @@ struct ixgbe_thermal_sensor_data {
|
||||
#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
|
||||
#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
|
||||
#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
|
||||
#define IXGBE_LVMMC_RX 0x2FA8
|
||||
#define IXGBE_LVMMC_TX 0x8108
|
||||
#define IXGBE_LMVM_RX 0x2FA4
|
||||
#define IXGBE_LMVM_TX 0x8124
|
||||
#define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) /* 4 total */
|
||||
#define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) /* 4 total */
|
||||
#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
|
||||
#define IXGBE_RXFECCERR0 0x051B8
|
||||
#define IXGBE_LLITHRESH 0x0EC90
|
||||
@ -350,8 +374,16 @@ struct ixgbe_thermal_sensor_data {
|
||||
#define IXGBE_IMIRVP 0x05AC0
|
||||
#define IXGBE_VMD_CTL 0x0581C
|
||||
#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
|
||||
#define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */
|
||||
#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
|
||||
|
||||
/* Registers for setting up RSS on X550 with SRIOV
|
||||
* _p - pool number (0..63)
|
||||
* _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
|
||||
*/
|
||||
#define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4))
|
||||
#define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40))
|
||||
#define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40))
|
||||
|
||||
/* Flow Director registers */
|
||||
#define IXGBE_FDIRCTRL 0x0EE00
|
||||
@ -405,6 +437,8 @@ struct ixgbe_thermal_sensor_data {
|
||||
#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
|
||||
#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
|
||||
#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
|
||||
#define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */
|
||||
#define IXGBE_DMATXCTL_MBINTEN 0x40 /* Bit 6 */
|
||||
#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
|
||||
|
||||
#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
|
||||
@ -436,16 +470,22 @@ struct ixgbe_thermal_sensor_data {
|
||||
|
||||
#define IXGBE_WUPL 0x05900
|
||||
#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
|
||||
#define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */
|
||||
#define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */
|
||||
#define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */
|
||||
|
||||
#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
|
||||
#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
|
||||
/* Ext Flexible Host Filter Table */
|
||||
#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100))
|
||||
#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100))
|
||||
#define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100))
|
||||
|
||||
/* Four Flexible Filters are supported */
|
||||
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
|
||||
|
||||
/* Six Flexible Filters are supported */
|
||||
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6
|
||||
/* Eight Flexible Filters are supported */
|
||||
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8 8
|
||||
#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
|
||||
|
||||
/* Each Flexible Filter is at most 128 (0x80) bytes in length */
|
||||
@ -478,10 +518,14 @@ struct ixgbe_thermal_sensor_data {
|
||||
#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
|
||||
#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
|
||||
#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
|
||||
#define IXGBE_WUFC_FLX_FILTERS_6 0x003F0000 /* Mask for 6 flex filters */
|
||||
#define IXGBE_WUFC_FLX_FILTERS_8 0x00FF0000 /* Mask for 8 flex filters */
|
||||
#define IXGBE_WUFC_FW_RST_WK 0x80000000 /* Ena wake on FW reset assertion */
|
||||
/* Mask for Ext. flex filters */
|
||||
#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
|
||||
#define IXGBE_WUFC_ALL_FILTERS 0x000F00FF /* Mask all 4 flex filters */
|
||||
#define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 flex filters */
|
||||
#define IXGBE_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 flex filters */
|
||||
#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
|
||||
|
||||
/* Wake Up Status */
|
||||
@ -501,6 +545,23 @@ struct ixgbe_thermal_sensor_data {
|
||||
#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
|
||||
#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
|
||||
#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
|
||||
#define IXGBE_WUS_FW_RST_WK IXGBE_WUFC_FW_RST_WK
|
||||
/* Proxy Status */
|
||||
#define IXGBE_PROXYS_EX 0x00000004 /* Exact packet received */
|
||||
#define IXGBE_PROXYS_ARP_DIR 0x00000020 /* ARP w/filter match received */
|
||||
#define IXGBE_PROXYS_NS 0x00000200 /* IPV6 NS received */
|
||||
#define IXGBE_PROXYS_NS_DIR 0x00000400 /* IPV6 NS w/DA match received */
|
||||
#define IXGBE_PROXYS_ARP 0x00000800 /* ARP request packet received */
|
||||
#define IXGBE_PROXYS_MLD 0x00001000 /* IPv6 MLD packet received */
|
||||
|
||||
/* Proxying Filter Control */
|
||||
#define IXGBE_PROXYFC_ENABLE 0x00000001 /* Port Proxying Enable */
|
||||
#define IXGBE_PROXYFC_EX 0x00000004 /* Directed Exact Proxy Enable */
|
||||
#define IXGBE_PROXYFC_ARP_DIR 0x00000020 /* Directed ARP Proxy Enable */
|
||||
#define IXGBE_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */
|
||||
#define IXGBE_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Enable */
|
||||
#define IXGBE_PROXYFC_MLD 0x00000800 /* IPv6 MLD Proxy Enable */
|
||||
#define IXGBE_PROXYFC_NO_TCO 0x00008000 /* Ignore TCO packets */
|
||||
|
||||
#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
|
||||
|
||||
@ -708,6 +769,8 @@ struct ixgbe_dmac_config {
|
||||
|
||||
|
||||
/* FCoE DMA Context Registers */
|
||||
/* FCoE Direct DMA Context */
|
||||
#define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
|
||||
#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
|
||||
#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
|
||||
#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
|
||||
@ -731,6 +794,12 @@ struct ixgbe_dmac_config {
|
||||
#define IXGBE_REOFF 0x05158 /* Rx FC EOF */
|
||||
#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
|
||||
/* FCoE Filter Context Registers */
|
||||
#define IXGBE_FCD_ID 0x05114 /* FCoE D_ID */
|
||||
#define IXGBE_FCSMAC 0x0510C /* FCoE Source MAC */
|
||||
#define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT 16
|
||||
/* FCoE Direct Filter Context */
|
||||
#define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
|
||||
#define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4))
|
||||
#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
|
||||
#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
|
||||
#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
|
||||
@ -761,6 +830,10 @@ struct ixgbe_dmac_config {
|
||||
#define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */
|
||||
#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
|
||||
#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
|
||||
#define IXGBE_FCRETA_SIZE_X550 32 /* Max entries in FCRETA */
|
||||
/* Higher 7 bits for the queue index */
|
||||
#define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000
|
||||
#define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16
|
||||
|
||||
/* Stats registers */
|
||||
#define IXGBE_CRCERRS 0x04000
|
||||
@ -880,6 +953,7 @@ struct ixgbe_dmac_config {
|
||||
#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
|
||||
|
||||
/* Management Bit Fields and Masks */
|
||||
#define IXGBE_MANC_MPROXYE 0x40000000 /* Management Proxy Enable */
|
||||
#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */
|
||||
#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */
|
||||
#define IXGBE_MANC_EN_BMC2OS_SHIFT 28
|
||||
@ -942,6 +1016,12 @@ struct ixgbe_dmac_config {
|
||||
#define IXGBE_PBACLR_82599 0x11068
|
||||
#define IXGBE_CIAA_82599 0x11088
|
||||
#define IXGBE_CIAD_82599 0x1108C
|
||||
#define IXGBE_CIAA_X550 0x11508
|
||||
#define IXGBE_CIAD_X550 0x11510
|
||||
#define IXGBE_CIAA_BY_MAC(_hw) ((((_hw)->mac.type >= ixgbe_mac_X550) ? \
|
||||
IXGBE_CIAA_X550 : IXGBE_CIAA_82599))
|
||||
#define IXGBE_CIAD_BY_MAC(_hw) ((((_hw)->mac.type >= ixgbe_mac_X550) ? \
|
||||
IXGBE_CIAD_X550 : IXGBE_CIAD_82599))
|
||||
#define IXGBE_PICAUSE 0x110B0
|
||||
#define IXGBE_PIENA 0x110B8
|
||||
#define IXGBE_CDQ_MBR_82599 0x110B4
|
||||
@ -978,6 +1058,7 @@ struct ixgbe_dmac_config {
|
||||
#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
|
||||
#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
|
||||
#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
|
||||
#define IXGBE_SYSTIMR 0x08C58 /* System time register Residue - RO */
|
||||
#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
|
||||
#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
|
||||
#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
|
||||
@ -994,6 +1075,9 @@ struct ixgbe_dmac_config {
|
||||
#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
|
||||
#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
|
||||
#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
|
||||
#define IXGBE_TSIM 0x08C68 /* TimeSync Interrupt Mask Register - RW */
|
||||
#define IXGBE_TSICR 0x08C60 /* TimeSync Interrupt Cause Register - WO */
|
||||
#define IXGBE_TSSDP 0x0003C /* TimeSync SDP Configuration Register - RW */
|
||||
|
||||
/* Diagnostic Registers */
|
||||
#define IXGBE_RDSTATCTL 0x02C20
|
||||
@ -1150,6 +1234,7 @@ struct ixgbe_dmac_config {
|
||||
/* RDRXCTL Bit Masks */
|
||||
#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */
|
||||
#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
|
||||
#define IXGBE_RDRXCTL_PSP 0x00000004 /* Pad Small Packet */
|
||||
#define IXGBE_RDRXCTL_MVMEN 0x00000020
|
||||
#define IXGBE_RDRXCTL_RSC_PUSH_DIS 0x00000020
|
||||
#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
|
||||
@ -1159,6 +1244,8 @@ struct ixgbe_dmac_config {
|
||||
#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/
|
||||
#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */
|
||||
#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */
|
||||
#define IXGBE_RDRXCTL_MBINTEN 0x10000000
|
||||
#define IXGBE_RDRXCTL_MDP_EN 0x20000000
|
||||
|
||||
/* RQTC Bit Masks and Shifts */
|
||||
#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
|
||||
@ -1337,6 +1424,7 @@ struct ixgbe_dmac_config {
|
||||
#define TN1010_PHY_ID 0x00A19410
|
||||
#define TNX_FW_REV 0xB
|
||||
#define X540_PHY_ID 0x01540200
|
||||
#define X550_PHY_ID 0x01540220
|
||||
#define AQ_FW_REV 0x20
|
||||
#define QT2022_PHY_ID 0x0043A400
|
||||
#define ATH_PHY_ID 0x03429050
|
||||
@ -1692,12 +1780,14 @@ enum {
|
||||
* 1588 (0x88f7): Filter 3
|
||||
* FIP (0x8914): Filter 4
|
||||
* LLDP (0x88CC): Filter 5
|
||||
* LACP (0x8809): Filter 6
|
||||
*/
|
||||
#define IXGBE_ETQF_FILTER_EAPOL 0
|
||||
#define IXGBE_ETQF_FILTER_FCOE 2
|
||||
#define IXGBE_ETQF_FILTER_1588 3
|
||||
#define IXGBE_ETQF_FILTER_FIP 4
|
||||
#define IXGBE_ETQF_FILTER_LLDP 5
|
||||
#define IXGBE_ETQF_FILTER_LACP 6
|
||||
/* VLAN Control Bit Masks */
|
||||
#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
|
||||
#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
|
||||
@ -1842,6 +1932,7 @@ enum {
|
||||
#define IXGBE_LINKS_TL_FAULT 0x00001000
|
||||
#define IXGBE_LINKS_SIGNAL 0x00000F00
|
||||
|
||||
#define IXGBE_LINKS_SPEED_NON_STD 0x08000000
|
||||
#define IXGBE_LINKS_SPEED_82599 0x30000000
|
||||
#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
|
||||
#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
|
||||
@ -1922,6 +2013,9 @@ enum {
|
||||
#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
|
||||
#define IXGBE_EEPROM_OPCODE_BITS 8
|
||||
|
||||
/* FLA Register */
|
||||
#define IXGBE_FLA_LOCKED 0x00000040
|
||||
|
||||
/* Part Number String Length */
|
||||
#define IXGBE_PBANUM_LENGTH 11
|
||||
|
||||
@ -1943,6 +2037,11 @@ enum {
|
||||
#define IXGBE_MAC1_PTR 0x0C
|
||||
#define IXGBE_CSR0_CONFIG_PTR 0x0D
|
||||
#define IXGBE_CSR1_CONFIG_PTR 0x0E
|
||||
#define IXGBE_PCIE_ANALOG_PTR_X550 0x02
|
||||
#define IXGBE_SHADOW_RAM_SIZE_X550 0x4000
|
||||
#define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24
|
||||
#define IXGBE_PCIE_CONFIG_SIZE 0x08
|
||||
#define IXGBE_EEPROM_LAST_WORD 0x41
|
||||
#define IXGBE_FW_PTR 0x0F
|
||||
#define IXGBE_PBANUM0_PTR 0x15
|
||||
#define IXGBE_PBANUM1_PTR 0x16
|
||||
@ -2155,6 +2254,14 @@ enum {
|
||||
#define IXGBE_TSAUXC_EN_CLK 0x00000004
|
||||
#define IXGBE_TSAUXC_SYNCLK 0x00000008
|
||||
#define IXGBE_TSAUXC_SDP0_INT 0x00000040
|
||||
#define IXGBE_TSAUXC_EN_TT0 0x00000001
|
||||
#define IXGBE_TSAUXC_EN_TT1 0x00000002
|
||||
#define IXGBE_TSAUXC_ST0 0x00000010
|
||||
#define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000
|
||||
|
||||
#define IXGBE_TSSDP_TS_SDP0_SEL_MASK 0x000000C0
|
||||
#define IXGBE_TSSDP_TS_SDP0_CLK0 0x00000080
|
||||
#define IXGBE_TSSDP_TS_SDP0_EN 0x00000100
|
||||
|
||||
#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
|
||||
#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */
|
||||
@ -2164,8 +2271,19 @@ enum {
|
||||
#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
|
||||
#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
|
||||
#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
|
||||
#define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08
|
||||
#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
|
||||
#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */
|
||||
#define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000 /* Rx Timestamp in Packet */
|
||||
#define IXGBE_TSYNCRXCTL_TSIP_UP_MASK 0xFF000000 /* Rx Timestamp UP Mask */
|
||||
|
||||
#define IXGBE_TSIM_SYS_WRAP 0x00000001
|
||||
#define IXGBE_TSIM_TXTS 0x00000002
|
||||
#define IXGBE_TSIM_TADJ 0x00000080
|
||||
|
||||
#define IXGBE_TSICR_SYS_WRAP IXGBE_TSIM_SYS_WRAP
|
||||
#define IXGBE_TSICR_TXTS IXGBE_TSIM_TXTS
|
||||
#define IXGBE_TSICR_TADJ IXGBE_TSIM_TADJ
|
||||
|
||||
#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
|
||||
#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
|
||||
@ -2224,10 +2342,12 @@ enum {
|
||||
#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
|
||||
#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
|
||||
#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
|
||||
#define IXGBE_MRQC_MULTIPLE_RSS 0x00002000
|
||||
#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
|
||||
|
||||
/* Queue Drop Enable */
|
||||
#define IXGBE_QDE_ENABLE 0x00000001
|
||||
#define IXGBE_QDE_HIDE_VLAN 0x00000002
|
||||
#define IXGBE_QDE_IDX_MASK 0x00007F00
|
||||
#define IXGBE_QDE_IDX_SHIFT 8
|
||||
#define IXGBE_QDE_WRITE 0x00010000
|
||||
@ -2269,10 +2389,12 @@ enum {
|
||||
#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
|
||||
#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
|
||||
#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
|
||||
#define IXGBE_RXD_STAT_OUTERIPCS 0x100 /* Cloud IP xsum calculated */
|
||||
#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
|
||||
#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
|
||||
#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
|
||||
#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
|
||||
#define IXGBE_RXD_STAT_TSIP 0x08000 /* Time Stamp in packet buffer */
|
||||
#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
|
||||
#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
|
||||
#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
|
||||
@ -2286,6 +2408,7 @@ enum {
|
||||
#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
|
||||
#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
|
||||
#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
|
||||
#define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000 /* CRC IP Header error */
|
||||
#define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */
|
||||
#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
|
||||
#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
|
||||
@ -2318,6 +2441,7 @@ enum {
|
||||
#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
|
||||
#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
|
||||
#define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */
|
||||
#define IXGBE_RXDADV_STAT_TSIP 0x00008000 /* Time Stamp in packet buffer */
|
||||
|
||||
/* PSRTYPE bit definitions */
|
||||
#define IXGBE_PSRTYPE_TCPHDR 0x00000010
|
||||
@ -2379,6 +2503,8 @@ enum {
|
||||
#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
|
||||
#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
|
||||
#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
|
||||
#define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */
|
||||
#define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */
|
||||
#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
|
||||
#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
|
||||
#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
|
||||
@ -2429,6 +2555,68 @@ enum {
|
||||
#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4))
|
||||
#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
|
||||
#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4))
|
||||
/* Translated register #defines */
|
||||
#define IXGBE_PVFCTRL(P) (0x00300 + (4 * (P)))
|
||||
#define IXGBE_PVFSTATUS(P) (0x00008 + (0 * (P)))
|
||||
#define IXGBE_PVFLINKS(P) (0x042A4 + (0 * (P)))
|
||||
#define IXGBE_PVFRTIMER(P) (0x00048 + (0 * (P)))
|
||||
#define IXGBE_PVFMAILBOX(P) (0x04C00 + (4 * (P)))
|
||||
#define IXGBE_PVFRXMEMWRAP(P) (0x03190 + (0 * (P)))
|
||||
#define IXGBE_PVTEICR(P) (0x00B00 + (4 * (P)))
|
||||
#define IXGBE_PVTEICS(P) (0x00C00 + (4 * (P)))
|
||||
#define IXGBE_PVTEIMS(P) (0x00D00 + (4 * (P)))
|
||||
#define IXGBE_PVTEIMC(P) (0x00E00 + (4 * (P)))
|
||||
#define IXGBE_PVTEIAC(P) (0x00F00 + (4 * (P)))
|
||||
#define IXGBE_PVTEIAM(P) (0x04D00 + (4 * (P)))
|
||||
#define IXGBE_PVTEITR(P) (((P) < 24) ? (0x00820 + ((P) * 4)) : \
|
||||
(0x012300 + (((P) - 24) * 4)))
|
||||
#define IXGBE_PVTIVAR(P) (0x12500 + (4 * (P)))
|
||||
#define IXGBE_PVTIVAR_MISC(P) (0x04E00 + (4 * (P)))
|
||||
#define IXGBE_PVTRSCINT(P) (0x12000 + (4 * (P)))
|
||||
#define IXGBE_VFPBACL(P) (0x110C8 + (4 * (P)))
|
||||
#define IXGBE_PVFRDBAL(P) ((P < 64) ? (0x01000 + (0x40 * (P))) \
|
||||
: (0x0D000 + (0x40 * ((P) - 64))))
|
||||
#define IXGBE_PVFRDBAH(P) ((P < 64) ? (0x01004 + (0x40 * (P))) \
|
||||
: (0x0D004 + (0x40 * ((P) - 64))))
|
||||
#define IXGBE_PVFRDLEN(P) ((P < 64) ? (0x01008 + (0x40 * (P))) \
|
||||
: (0x0D008 + (0x40 * ((P) - 64))))
|
||||
#define IXGBE_PVFRDH(P) ((P < 64) ? (0x01010 + (0x40 * (P))) \
|
||||
: (0x0D010 + (0x40 * ((P) - 64))))
|
||||
#define IXGBE_PVFRDT(P) ((P < 64) ? (0x01018 + (0x40 * (P))) \
|
||||
: (0x0D018 + (0x40 * ((P) - 64))))
|
||||
#define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \
|
||||
: (0x0D028 + (0x40 * ((P) - 64))))
|
||||
#define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \
|
||||
: (0x0D014 + (0x40 * ((P) - 64))))
|
||||
#define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P)))
|
||||
#define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P)))
|
||||
#define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P)))
|
||||
#define IXGBE_PVFTTDLEN(P) (0x06008 + (0x40 * (P)))
|
||||
#define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P)))
|
||||
#define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P)))
|
||||
#define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P)))
|
||||
#define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P)))
|
||||
#define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P)))
|
||||
#define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \
|
||||
: (0x0D00C + (0x40 * ((P) - 64))))
|
||||
#define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P)))
|
||||
#define IXGBE_PVFGPRC(x) (0x0101C + (0x40 * (x)))
|
||||
#define IXGBE_PVFGPTC(x) (0x08300 + (0x04 * (x)))
|
||||
#define IXGBE_PVFGORC_LSB(x) (0x01020 + (0x40 * (x)))
|
||||
#define IXGBE_PVFGORC_MSB(x) (0x0D020 + (0x40 * (x)))
|
||||
#define IXGBE_PVFGOTC_LSB(x) (0x08400 + (0x08 * (x)))
|
||||
#define IXGBE_PVFGOTC_MSB(x) (0x08404 + (0x08 * (x)))
|
||||
#define IXGBE_PVFMPRC(x) (0x0D01C + (0x40 * (x)))
|
||||
|
||||
#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
|
||||
(IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
|
||||
#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
|
||||
(IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
|
||||
|
||||
#define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \
|
||||
(IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
|
||||
#define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \
|
||||
(IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
|
||||
|
||||
/* Little Endian defines */
|
||||
#ifndef __le16
|
||||
@ -2552,7 +2740,17 @@ enum ixgbe_fdir_pballoc_type {
|
||||
#define FW_CEM_UNUSED_VER 0x0
|
||||
#define FW_CEM_MAX_RETRIES 3
|
||||
#define FW_CEM_RESP_STATUS_SUCCESS 0x1
|
||||
|
||||
#define FW_READ_SHADOW_RAM_CMD 0x31
|
||||
#define FW_READ_SHADOW_RAM_LEN 0x6
|
||||
#define FW_WRITE_SHADOW_RAM_CMD 0x33
|
||||
#define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */
|
||||
#define FW_SHADOW_RAM_DUMP_CMD 0x36
|
||||
#define FW_SHADOW_RAM_DUMP_LEN 0
|
||||
#define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
|
||||
#define FW_NVM_DATA_OFFSET 3
|
||||
#define FW_MAX_READ_BUFFER_SIZE 1024
|
||||
#define FW_DISABLE_RXEN_CMD 0xDE
|
||||
#define FW_DISABLE_RXEN_LEN 0x1
|
||||
/* Host Interface Command Structures */
|
||||
|
||||
struct ixgbe_hic_hdr {
|
||||
@ -2565,6 +2763,13 @@ struct ixgbe_hic_hdr {
|
||||
u8 checksum;
|
||||
};
|
||||
|
||||
struct ixgbe_hic_hdr2 {
|
||||
u8 cmd;
|
||||
u8 buf_len1;
|
||||
u8 buf_len2;
|
||||
u8 checksum;
|
||||
};
|
||||
|
||||
struct ixgbe_hic_drv_info {
|
||||
struct ixgbe_hic_hdr hdr;
|
||||
u8 port_num;
|
||||
@ -2576,6 +2781,33 @@ struct ixgbe_hic_drv_info {
|
||||
u16 pad2; /* end spacing to ensure length is mult. of dword2 */
|
||||
};
|
||||
|
||||
/* These need to be dword aligned */
|
||||
struct ixgbe_hic_read_shadow_ram {
|
||||
struct ixgbe_hic_hdr2 hdr;
|
||||
u32 address;
|
||||
u16 length;
|
||||
u16 pad2;
|
||||
u16 data;
|
||||
u16 pad3;
|
||||
};
|
||||
|
||||
struct ixgbe_hic_write_shadow_ram {
|
||||
struct ixgbe_hic_hdr2 hdr;
|
||||
u32 address;
|
||||
u16 length;
|
||||
u16 pad2;
|
||||
u16 data;
|
||||
u16 pad3;
|
||||
};
|
||||
|
||||
struct ixgbe_hic_disable_rxen {
|
||||
struct ixgbe_hic_hdr hdr;
|
||||
u8 port_number;
|
||||
u8 pad2;
|
||||
u16 pad3;
|
||||
};
|
||||
|
||||
|
||||
/* Transmit Descriptor - Legacy */
|
||||
struct ixgbe_legacy_tx_desc {
|
||||
u64 buffer_addr; /* Address of the descriptor's data buffer */
|
||||
@ -2717,6 +2949,12 @@ struct ixgbe_adv_tx_context_desc {
|
||||
#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
|
||||
#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
|
||||
|
||||
#define IXGBE_ADVTXD_OUTER_IPLEN 16 /* Adv ctxt OUTERIPLEN shift */
|
||||
#define IXGBE_ADVTXD_TUNNEL_LEN 24 /* Adv ctxt TUNNELLEN shift */
|
||||
#define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16 /* Adv Tx Desc Tunnel Type shift */
|
||||
#define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17 /* Adv Tx Desc OUTERIPCS Shift */
|
||||
#define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1 /* Adv Tx Desc Tunnel Type NVGRE */
|
||||
|
||||
/* Autonegotiation advertised speeds */
|
||||
typedef u32 ixgbe_autoneg_advertised;
|
||||
/* Link speed */
|
||||
@ -2724,6 +2962,7 @@ typedef u32 ixgbe_link_speed;
|
||||
#define IXGBE_LINK_SPEED_UNKNOWN 0
|
||||
#define IXGBE_LINK_SPEED_100_FULL 0x0008
|
||||
#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
|
||||
#define IXGBE_LINK_SPEED_2_5GB_FULL 0x0040
|
||||
#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
|
||||
#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
|
||||
IXGBE_LINK_SPEED_10GB_FULL)
|
||||
@ -2920,6 +3159,15 @@ enum ixgbe_mac_type {
|
||||
ixgbe_mac_82599_vf,
|
||||
ixgbe_mac_X540,
|
||||
ixgbe_mac_X540_vf,
|
||||
/*
|
||||
* X550EM MAC type decoder:
|
||||
* ixgbe_mac_X550EM_x: "x" = Xeon
|
||||
* ixgbe_mac_X550EM_a: "a" = Atom
|
||||
*/
|
||||
ixgbe_mac_X550,
|
||||
ixgbe_mac_X550EM_x,
|
||||
ixgbe_mac_X550_vf,
|
||||
ixgbe_mac_X550EM_x_vf,
|
||||
ixgbe_num_macs
|
||||
};
|
||||
|
||||
@ -2928,6 +3176,8 @@ enum ixgbe_phy_type {
|
||||
ixgbe_phy_none,
|
||||
ixgbe_phy_tn,
|
||||
ixgbe_phy_aq,
|
||||
ixgbe_phy_x550em_kr,
|
||||
ixgbe_phy_x550em_kx4,
|
||||
ixgbe_phy_cu_unknown,
|
||||
ixgbe_phy_qt,
|
||||
ixgbe_phy_xaui,
|
||||
@ -3455,6 +3705,44 @@ struct ixgbe_hw {
|
||||
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
|
||||
|
||||
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P == 0) ? (0x4010) : (0x8010))
|
||||
#define IXGBE_KRM_LINK_CTRL_1(P) ((P == 0) ? (0x420C) : (0x820C))
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P == 0) ? (0x4634) : (0x8634))
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P == 0) ? (0x4638) : (0x8638))
|
||||
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P == 0) ? (0x4B00) : (0x8B00))
|
||||
#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P == 0) ? (0x4E00) : (0x8E00))
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P == 0) ? (0x5520) : (0x9520))
|
||||
#define IXGBE_KRM_RX_ANA_CTL(P) ((P == 0) ? (0x5A00) : (0x9A00))
|
||||
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
|
||||
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
|
||||
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)
|
||||
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
|
||||
|
||||
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
|
||||
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)
|
||||
|
||||
#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)
|
||||
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1)
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2)
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3)
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31)
|
||||
|
||||
#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
|
||||
#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
|
||||
|
||||
|
||||
@ -84,6 +84,9 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define IXGBE_VFGOTC_LSB 0x02020
|
||||
#define IXGBE_VFGOTC_MSB 0x02024
|
||||
#define IXGBE_VFMPRC 0x01034
|
||||
#define IXGBE_VFMRQC 0x3000
|
||||
#define IXGBE_VFRSSRK(x) (0x3100 + ((x) * 4))
|
||||
#define IXGBE_VFRETA(x) (0x3200 + ((x) * 4))
|
||||
|
||||
|
||||
struct ixgbevf_hw_stats {
|
||||
|
||||
1809
lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c
Normal file
1809
lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c
Normal file
File diff suppressed because it is too large
Load Diff
88
lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.h
Normal file
88
lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.h
Normal file
@ -0,0 +1,88 @@
|
||||
/*******************************************************************************
|
||||
|
||||
Copyright (c) 2001-2014, Intel Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef _IXGBE_X550_H_
|
||||
#define _IXGBE_X550_H_
|
||||
|
||||
#include "ixgbe_type.h"
|
||||
|
||||
s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
|
||||
u16 *checksum_val);
|
||||
s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
|
||||
u16 offset, u16 words, u16 *data);
|
||||
s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
|
||||
u16 data);
|
||||
s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
|
||||
u16 offset, u16 words, u16 *data);
|
||||
s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
|
||||
u16 *data);
|
||||
s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
|
||||
u16 *data);
|
||||
s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
|
||||
u16 data);
|
||||
s32 ixgbe_set_eee_X550(struct ixgbe_hw *hw, bool enable_eee);
|
||||
s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee);
|
||||
void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
|
||||
unsigned int pool);
|
||||
void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
|
||||
bool enable, int vf);
|
||||
s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
u32 device_type, u32 data);
|
||||
s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
u32 device_type, u32 *data);
|
||||
void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw);
|
||||
void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw);
|
||||
void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap);
|
||||
void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf);
|
||||
enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
|
||||
ixgbe_link_speed *speed, bool *autoneg);
|
||||
void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw);
|
||||
u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw);
|
||||
void ixgbe_disable_rx_x550(struct ixgbe_hw *hw);
|
||||
#endif /* _IXGBE_X550_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user