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net/e1000/base: modify HW level time sync mechanisms

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Add additional configuration space access to allow HW
level time sync mechanism.

Signed-off-by: Evgeny Efimov <evgeny.efimov@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>
This commit is contained in:
Guinan Sun 2020-07-06 08:12:04 +00:00 committed by Ferruh Yigit
parent b8592c89c8
commit d53391f1fe
2 changed files with 19 additions and 0 deletions
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18
drivers/net/e1000/base/e1000_ich8lan.c
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@ -4896,6 +4896,7 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
u16 kum_cfg;
u32 ctrl, reg;
s32 ret_val;
u16 pci_cfg;
DEBUGFUNC("e1000_reset_hw_ich8lan");
@ -4956,11 +4957,28 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
e1000_gate_hw_phy_config_ich8lan(hw, true);
}
ret_val = e1000_acquire_swflag_ich8lan(hw);
/* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
* may occur during global reset and cause system hang.
* Configuration space access creates the needed delay.
* Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
* insures configuration space read is done before global reset.
*/
e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
DEBUGOUT("Issuing a global reset to ich8lan\n");
E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
/* cannot issue a flush here because it hangs the hardware */
msec_delay(20);
/* Configuration space access improve HW level time sync mechanism.
* Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
* value to insure configuration space read is done
* before any access to mac register.
*/
e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
/* Set Phy Config Counter to 50msec */
if (hw->mac.type == e1000_pch2lan) {
reg = E1000_READ_REG(hw, E1000_FEXTNVM3);

1
drivers/net/e1000/base/e1000_ich8lan.h
View File

@ -287,6 +287,7 @@
/* Receive Address Initial CRC Calculation */
#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
#define E1000_PCI_VENDOR_ID_REGISTER 0x00
#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
#define E1000_PCI_REVISION_ID_REG 0x08
#endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */