net/i40e/base: support FCoE
Add Fibre Channel Over Ethernet (FCoE) in PHY capabilities. Add data structure for FCoE statistics collection. Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
This commit is contained in:
Qi Zhang
Bruce Richardson
parent
fc1d8b8a16
commit
d536192e7c
@ -1768,6 +1768,8 @@ struct i40e_aq_get_phy_abilities_resp {
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#define I40E_AQ_PHY_LINK_ENABLED 0x08
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#define I40E_AQ_PHY_AN_ENABLED 0x10
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#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
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#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
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#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
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__le16 eee_capability;
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#define I40E_AQ_EEE_100BASE_TX 0x0002
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#define I40E_AQ_EEE_1000BASE_T 0x0004
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@ -1811,7 +1813,13 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */
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#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
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#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
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#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
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u8 reserved[2];
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u8 fec_config;
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#define I40E_AQ_SET_FEC_ABILITY_KR (1 << 0)
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#define I40E_AQ_SET_FEC_ABILITY_RS (1 << 1)
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#define I40E_AQ_SET_FEC_REQUEST_KR (1 << 2)
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#define I40E_AQ_SET_FEC_REQUEST_RS (1 << 3)
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#define I40E_AQ_SET_FEC_AUTO (1 << 4)
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u8 reserved;
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};
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I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
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@ -1901,6 +1909,8 @@ struct i40e_aqc_get_link_status {
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u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
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__le16 max_frame_size;
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u8 config;
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#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
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#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
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#define I40E_AQ_CONFIG_CRC_ENA 0x04
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#define I40E_AQ_CONFIG_PACING_MASK 0x78
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u8 power_desc;
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@ -1392,6 +1392,23 @@ struct i40e_veb_tc_stats {
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u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
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};
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/* Statistics collected per function for FCoE */
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struct i40e_fcoe_stats {
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u64 rx_fcoe_packets; /* fcoeprc */
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u64 rx_fcoe_dwords; /* focedwrc */
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u64 rx_fcoe_dropped; /* fcoerpdc */
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u64 tx_fcoe_packets; /* fcoeptc */
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u64 tx_fcoe_dwords; /* focedwtc */
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u64 fcoe_bad_fccrc; /* fcoecrc */
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u64 fcoe_last_error; /* fcoelast */
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u64 fcoe_ddp_count; /* fcoeddpc */
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};
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/* offset to per function FCoE statistics block */
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#define I40E_FCOE_VF_STAT_OFFSET 0
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#define I40E_FCOE_PF_STAT_OFFSET 128
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#define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
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/* Statistics collected by the MAC */
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struct i40e_hw_port_stats {
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/* eth stats collected by the port */
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@ -1513,6 +1530,208 @@ struct i40e_hw_port_stats {
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#define I40E_SRRD_SRCTL_ATTEMPTS 100000
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/* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
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enum i40E_fcoe_tx_ctx_desc_cmd_bits {
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I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
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I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
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I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
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I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
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I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
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I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
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I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
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I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
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I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
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I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
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I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
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I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
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I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
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};
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/* FCoE DIF/DIX Context descriptor */
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struct i40e_fcoe_difdix_context_desc {
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__le64 flags_buff0_buff1_ref;
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__le64 difapp_msk_bias;
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};
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#define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
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#define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
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I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
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enum i40e_fcoe_difdix_ctx_desc_flags_bits {
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
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/* 1 BIT */
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I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
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/* 1 BIT */
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I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
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/* 1 BIT */
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I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
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/* 1 BIT */
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I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
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/* 2 BITS */
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I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
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/* 1 BIT */
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I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
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/* 1 BIT */
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I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
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/* 1 BIT */
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I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
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/* 1 BIT */
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I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
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};
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#define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
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#define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
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I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
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#define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
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#define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
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I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
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#define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
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#define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
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I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
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#define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
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#define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
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I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
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#define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
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#define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
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I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
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#define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
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#define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
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I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
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/* FCoE DIF/DIX Buffers descriptor */
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struct i40e_fcoe_difdix_buffers_desc {
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__le64 buff_addr0;
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__le64 buff_addr1;
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};
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/* FCoE DDP Context descriptor */
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struct i40e_fcoe_ddp_context_desc {
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__le64 rsvd;
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__le64 type_cmd_foff_lsize;
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};
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#define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
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#define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
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I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
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#define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
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#define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
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I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
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enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
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I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
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I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
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I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
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I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
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I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
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I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
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};
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#define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
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#define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
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I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
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#define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
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#define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
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I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
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/* FCoE DDP/DWO Queue Context descriptor */
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struct i40e_fcoe_queue_context_desc {
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__le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
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__le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
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};
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#define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
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#define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
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I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
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#define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
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#define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
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I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
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#define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
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#define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
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I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
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#define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
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#define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
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I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
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enum i40e_fcoe_queue_ctx_desc_tph_bits {
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I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
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I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
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};
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#define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
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#define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
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I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
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/* FCoE DDP/DWO Filter Context descriptor */
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struct i40e_fcoe_filter_context_desc {
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__le32 param;
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__le16 seqn;
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/* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
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__le16 rsvd_dmaindx;
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/* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
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__le64 flags_rsvd_lanq;
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};
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#define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
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#define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
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I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
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enum i40e_fcoe_filter_ctx_desc_flags_bits {
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I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
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I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
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I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
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I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
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I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
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I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
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};
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#define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
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#define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
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I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
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#define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
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#define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
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I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
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#define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
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#define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
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I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
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enum i40e_switch_element_types {
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I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
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I40E_SWITCH_ELEMENT_TYPE_PF = 2,
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