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net/qede: fix ethernet type in HW registers

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Fix to program the HW registers with proper ether type.

Fixes: 36f45bce25 ("net/qede/base: fix to support OVLAN mode")
Cc: stable@dpdk.org

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
This commit is contained in:
Rasesh Mody 2018-09-08 13:30:53 -07:00 committed by Ferruh Yigit
parent 4fe58a3ecf
commit d5df6159dd
1 changed files with 20 additions and 0 deletions
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20
drivers/net/qede/base/ecore_dev.c
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@ -2410,6 +2410,7 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
bool b_default_mtu = true;
struct ecore_hwfn *p_hwfn;
enum _ecore_status_t rc = ECORE_SUCCESS;
u16 ether_type;
int i;
if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
@ -2442,6 +2443,25 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
if (rc != ECORE_SUCCESS)
return rc;
if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
&p_dev->mf_bits) ||
OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
&p_dev->mf_bits))) {
if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
&p_dev->mf_bits))
ether_type = ETHER_TYPE_VLAN;
else
ether_type = ETHER_TYPE_QINQ;
STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
ether_type);
STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
ether_type);
STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
ether_type);
STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
ether_type);
}
ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,