net/ice/base: ensure only valid bits are set
In the ice_aq_set_phy_cfg AQ command, the 16.4 bit is reserved. This patch will make sure that this bit will never be set to 1. Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com> Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Reviewed-by: Qiming Yang <qiming.yang@intel.com> Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
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@ -1327,6 +1327,7 @@ struct ice_aqc_set_phy_cfg_data {
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__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
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__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
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u8 caps;
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#define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
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#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
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#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
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#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
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@ -2351,6 +2351,15 @@ ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
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if (!cfg)
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return ICE_ERR_PARAM;
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/* Ensure that only valid bits of cfg->caps can be turned on. */
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if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
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ice_debug(hw, ICE_DBG_PHY,
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"Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
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cfg->caps);
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cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
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}
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ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
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desc.params.set_phy.lport_num = lport;
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desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
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