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net/cxgbe: set default PCIe completion timeout

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Program the PCIe completion timeout to 4 sec to give enough time
to allow completions to be received successfully in some older systems.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
This commit is contained in:
Rahul Lakkireddy 2016-05-06 13:13:17 +05:30 committed by Bruce Richardson
parent 5c81b1a9e8
commit d90c196150
2 changed files with 20 additions and 1 deletions
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2
drivers/net/cxgbe/base/adapter.h
View File

@ -431,8 +431,10 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_CAPABILITY_LIST 0x34
/* Offset of first capability list entry */
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
/**
* t4_os_pci_write_cfg4 - 32-bit write to PCI config space

19
drivers/net/cxgbe/base/t4_hw.c
View File

@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
* Copyright(c) 2014-2015 Chelsio Communications.
* Copyright(c) 2014-2016 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -2326,6 +2326,21 @@ int t4_get_flash_params(struct adapter *adapter)
return 0;
}
static void set_pcie_completion_timeout(struct adapter *adapter,
u8 range)
{
u32 pcie_cap;
u16 val;
pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
if (pcie_cap) {
t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
val &= 0xfff0;
val |= range;
t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
}
}
/**
* t4_prep_adapter - prepare SW and HW for operation
* @adapter: the adapter
@ -2384,6 +2399,8 @@ int t4_prep_adapter(struct adapter *adapter)
adapter->params.portvec = 1;
adapter->params.vpd.cclk = 50000;
/* Set pci completion timeout value to 4 seconds. */
set_pcie_completion_timeout(adapter, 0xd);
return 0;
}