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config: change defaults of armv8

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Current default cache line size for armv8 CPUs having Implementor ID of
0x41 is 128 bytes, changing it to 64 bytes. Also, the max number of lcores
is changed to 16 from 256.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
This commit is contained in:
Yongseok Koh 2019-04-18 04:49:01 -07:00 committed by Thomas Monjalon
parent d588f12ffb
commit d97108a332
1 changed files with 6 additions and 1 deletions
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7
config/arm/meson.build
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@ -33,6 +33,11 @@ flags_generic = [
['RTE_MAX_LCORE', 256],
['RTE_USE_C11_MEM_MODEL', true],
['RTE_CACHE_LINE_SIZE', 128]]
flags_arm = [
['RTE_MACHINE', '"armv8a"'],
['RTE_MAX_LCORE', 16],
['RTE_USE_C11_MEM_MODEL', true],
['RTE_CACHE_LINE_SIZE', 64]]
flags_cavium = [
['RTE_CACHE_LINE_SIZE', 128],
['RTE_MAX_NUMA_NODES', 2],
@ -89,7 +94,7 @@ machine_args_cavium = [
## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
impl_0x41 = ['Arm', flags_generic, machine_args_generic]
impl_0x41 = ['Arm', flags_arm, machine_args_generic]
impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
impl_0x44 = ['DEC', flags_generic, machine_args_generic]