net/igc: support I226 devices
Added I226 Series device ID in igc driver and updated igc guide document for new devices. Signed-off-by: Qiming Yang <qiming.yang@intel.com> Signed-off-by: Kevin Liu <kevinx.liu@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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@ -5,11 +5,12 @@ IGC Poll Mode Driver
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======================
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The IGC PMD (**librte_net_igc**) provides poll mode driver support for Foxville
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I225 Series Network Adapters.
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I225 and I226 Series Network Adapters.
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- For information about I225, please refer to: `Intel® Ethernet Controller I225 Series
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<https://ark.intel.com/content/www/us/en/ark/products/series/184686/intel-ethernet-controller-i225-series.html>`_.
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- For information about I226, please refer to: `Intel® Ethernet Controller I226 Series
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<https://ark.intel.com/content/www/us/en/ark/products/series/210588/intel-ethernet-controller-i226-series.html>`_.
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Driver compilation and testing
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------------------------------
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@ -21,11 +22,10 @@ for details.
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Supported Chipsets and NICs
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---------------------------
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Foxville LM (I225 LM): Client 2.5G LAN vPro Corporate
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Foxville V (I225 V): Client 2.5G LAN Consumer
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Foxville I (I225 I): Client 2.5G Industrial Temp
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Foxville V (I225 K): Client 2.5G LAN Consumer
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Foxville LM (I225 LM, I226 LM): Client 2.5G LAN vPro Corporate
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Foxville V (I225 V, I226 V): Client 2.5G LAN Consumer
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Foxville I (I225 I, I226 IM): Client 2.5G Industrial Temp
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Foxville V (I225 K, I226 K): Client 2.5G LAN Consumer
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Sample Application Notes
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------------------------
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@ -106,6 +106,11 @@ New Features
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* Added Tx QoS queue / queue group priority configuration support.
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* Added Tx QoS queue weight configuration support.
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* **Updated Intel igc driver.**
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Added Intel Foxville I226 devices in ``igc`` driver.
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See the doc:`../nics/igc` NIC guide for more details.
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* **Updated Mellanox mlx5 driver.**
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* Added support for promiscuous mode on Windows.
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@ -888,6 +888,12 @@ s32 igc_set_mac_type(struct igc_hw *hw)
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case IGC_DEV_ID_I225_I:
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case IGC_DEV_ID_I220_V:
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case IGC_DEV_ID_I225_BLANK_NVM:
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case IGC_DEV_ID_I226_K:
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case IGC_DEV_ID_I226_LMVP:
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case IGC_DEV_ID_I226_LM:
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case IGC_DEV_ID_I226_V:
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case IGC_DEV_ID_I226_IT:
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case IGC_DEV_ID_I226_BLANK_NVM:
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mac->type = igc_i225;
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break;
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case IGC_DEV_ID_I350_VF:
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@ -1351,6 +1351,7 @@
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#define IGP04IGC_E_PHY_ID 0x02A80391
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#define M88_VENDOR 0x0141
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#define I225_I_PHY_ID 0x67C9DC00
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#define I226_LM_PHY_ID 0x67C9DC10
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/* M88E1000 Specific Registers */
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#define M88IGC_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
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@ -166,6 +166,12 @@ struct igc_hw;
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#define IGC_DEV_ID_I225_I 0x15F8
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#define IGC_DEV_ID_I220_V 0x15F7
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#define IGC_DEV_ID_I225_BLANK_NVM 0x15FD
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#define IGC_DEV_ID_I226_K 0x3102
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#define IGC_DEV_ID_I226_LMVP 0x5503
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#define IGC_DEV_ID_I226_LM 0x125B
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#define IGC_DEV_ID_I226_V 0x125C
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#define IGC_DEV_ID_I226_IT 0x125D
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#define IGC_DEV_ID_I226_BLANK_NVM 0x125F
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#define IGC_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
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#define IGC_DEV_ID_I354_SGMII 0x1F41
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#define IGC_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
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@ -176,6 +176,7 @@ static s32 igc_init_phy_params_i225(struct igc_hw *hw)
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/* Verify phy id and set remaining function pointers */
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switch (phy->id) {
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case I225_I_PHY_ID:
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case I226_LM_PHY_ID:
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phy->type = igc_phy_i225;
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phy->ops.set_d0_lplu_state = igc_set_d0_lplu_state_i225;
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phy->ops.set_d3_lplu_state = igc_set_d3_lplu_state_i225;
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@ -97,6 +97,12 @@ static const struct rte_pci_id pci_id_igc_map[] = {
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_V) },
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_I) },
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_K) },
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I226_K) },
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I226_LMVP) },
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I226_LM) },
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I226_V) },
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I226_IT) },
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I226_BLANK_NVM) },
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{ .vendor_id = 0, /* sentinel */ },
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};
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