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ring: remove split cacheline build setting

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Users compiling DPDK should not need to know or care about the arrangement
of cachelines in the rte_ring structure.  Therefore just remove the build
option and set the structures to be always split. On platforms with 64B
cachelines, for improved performance use 128B rather than 64B alignment
since it stops the producer and consumer data being on adjacent cachelines.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
This commit is contained in:
Bruce Richardson 2017-03-29 16:21:17 +01:00 committed by Thomas Monjalon
parent 05cc9fec45
commit d9f0d3a1ff
4 changed files with 17 additions and 9 deletions
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1
config/common_base
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@ -453,7 +453,6 @@ CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y
#
CONFIG_RTE_LIBRTE_RING=y
CONFIG_RTE_LIBRTE_RING_DEBUG=n
CONFIG_RTE_RING_SPLIT_PROD_CONS=n
CONFIG_RTE_RING_PAUSE_REP_COUNT=0
#

7
doc/guides/rel_notes/release_17_05.rst
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@ -127,6 +127,13 @@ API Changes
* The LPM ``next_hop`` field is extended from 8 bits to 21 bits for IPv6
while keeping ABI compatibility.
* **Reworked rte_ring library**
The rte_ring library has been reworked and updated. The following changes
have been made to it:
* removed the build-time setting ``CONFIG_RTE_RING_SPLIT_PROD_CONS``
ABI Changes
-----------

2
lib/librte_ring/rte_ring.c
View File

@ -127,10 +127,8 @@ rte_ring_init(struct rte_ring *r, const char *name, unsigned count,
/* compilation-time checks */
RTE_BUILD_BUG_ON((sizeof(struct rte_ring) &
RTE_CACHE_LINE_MASK) != 0);
#ifdef RTE_RING_SPLIT_PROD_CONS
RTE_BUILD_BUG_ON((offsetof(struct rte_ring, cons) &
RTE_CACHE_LINE_MASK) != 0);
#endif
RTE_BUILD_BUG_ON((offsetof(struct rte_ring, prod) &
RTE_CACHE_LINE_MASK) != 0);
#ifdef RTE_LIBRTE_RING_DEBUG

16
lib/librte_ring/rte_ring.h
View File

@ -139,6 +139,14 @@ struct rte_ring_debug_stats {
struct rte_memzone; /* forward declaration, so as not to require memzone.h */
#if RTE_CACHE_LINE_SIZE < 128
#define PROD_ALIGN (RTE_CACHE_LINE_SIZE * 2)
#define CONS_ALIGN (RTE_CACHE_LINE_SIZE * 2)
#else
#define PROD_ALIGN RTE_CACHE_LINE_SIZE
#define CONS_ALIGN RTE_CACHE_LINE_SIZE
#endif
/**
* An RTE ring structure.
*
@ -168,7 +176,7 @@ struct rte_ring {
uint32_t mask; /**< Mask (size-1) of ring. */
volatile uint32_t head; /**< Producer head. */
volatile uint32_t tail; /**< Producer tail. */
} prod __rte_cache_aligned;
} prod __rte_aligned(PROD_ALIGN);
/** Ring consumer status. */
struct cons {
@ -177,11 +185,7 @@ struct rte_ring {
uint32_t mask; /**< Mask (size-1) of ring. */
volatile uint32_t head; /**< Consumer head. */
volatile uint32_t tail; /**< Consumer tail. */
#ifdef RTE_RING_SPLIT_PROD_CONS
} cons __rte_cache_aligned;
#else
} cons;
#endif
} cons __rte_aligned(CONS_ALIGN);
#ifdef RTE_LIBRTE_RING_DEBUG
struct rte_ring_debug_stats stats[RTE_MAX_LCORE];