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net/mlx5: support checksum offload on Windows

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Support of the checksum offloading by checking
the relevant FW capability (csum_cap) for NIC support.

RX supported offloads:

DEV_RX_OFFLOAD_IPV4_CKSUM
DEV_RX_OFFLOAD_UDP_CKSUM
DEV_RX_OFFLOAD_TCP_CKSUM

TX supported offloads:

DEV_TX_OFFLOAD_IPV4_CKSUM
DEV_TX_OFFLOAD_UDP_CKSUM
DEV_TX_OFFLOAD_TCP_CKSUM

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: Odi Assli <odia@nvidia.com>
This commit is contained in:
Tal Shnaiderman 2021-04-21 19:34:41 +03:00 committed by Raslan Darawsheh
parent 11e61a9467
commit db16bbfb5c
1 changed files with 3 additions and 2 deletions
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5
drivers/net/mlx5/windows/mlx5_os.c
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@ -420,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
err = mlx5_dev_check_sibling_config(priv, config);
if (err)
goto error;
DRV_LOG(DEBUG, "checksum offloading is %ssupported",
(config->hw_csum ? "" : "not "));
DRV_LOG(DEBUG, "counters are not supported");
config->ind_table_max_size =
sh->device_attr.max_rwq_indirection_table_size;
@ -464,6 +462,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
sh->cmng.relaxed_ordering_read =
config->hca_attr.relaxed_ordering_read;
}
config->hw_csum = config->hca_attr.csum_cap;
DRV_LOG(DEBUG, "checksum offloading is %ssupported",
(config->hw_csum ? "" : "not "));
}
if (config->devx) {
uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];