net/bnx2x: merge debug register operations into headers
The register read/writes should just be static inline instead of
alternately defined as routines or macros depending on the status of
debugging.
Fix bnx2x_reg_read32() returning 0 during debug unaligned reads.
Fixes: b5bf7719221d ("bnx2x: driver support routines")
Signed-off-by: Chas Williams <3chas3@gmail.com>
Acked-by: Harish Patil <harish.patil@qlogic.com>
This commit is contained in:
Chas Williams
Bruce Richardson
parent
039d213129
commit
dc687592ac
@ -28,7 +28,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_ethdev.c
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SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += ecore_sp.c
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SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += elink.c
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SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_vfpf.c
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SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC) += debug.c
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# this lib depends upon:
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DEPDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += lib/librte_eal lib/librte_ether
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@ -1414,33 +1414,94 @@ struct bnx2x_func_init_params {
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#define BAR1 2
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#define BAR2 4
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static inline void
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bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
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{
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
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(unsigned long)offset, val);
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*((volatile uint8_t*)
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((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
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}
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static inline void
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bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
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{
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#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
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uint8_t bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset);
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uint16_t bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset);
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uint32_t bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset);
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void bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val);
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void bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val);
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void bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val);
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#else
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#define bnx2x_reg_write8(sc, offset, val)\
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*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val
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#define bnx2x_reg_write16(sc, offset, val)\
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*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val
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#define bnx2x_reg_write32(sc, offset, val)\
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*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val
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#define bnx2x_reg_read8(sc, offset)\
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(*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))
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#define bnx2x_reg_read16(sc, offset)\
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(*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))
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#define bnx2x_reg_read32(sc, offset)\
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(*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)))
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if ((offset % 2) != 0)
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PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx",
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(unsigned long)offset);
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#endif
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x",
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(unsigned long)offset, val);
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*((volatile uint16_t*)
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((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
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}
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static inline void
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bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
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{
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#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
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if ((offset % 4) != 0)
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PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx",
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(unsigned long)offset);
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#endif
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
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(unsigned long)offset, val);
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*((volatile uint32_t*)
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((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
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}
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static inline uint8_t
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bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
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{
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uint8_t val;
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val = (uint8_t)(*((volatile uint8_t*)
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((uintptr_t)sc->bar[BAR0].base_addr + offset)));
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
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(unsigned long)offset, val);
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return val;
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}
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static inline uint16_t
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bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
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{
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uint16_t val;
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#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
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if ((offset % 2) != 0)
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PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx",
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(unsigned long)offset);
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#endif
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val = (uint16_t)(*((volatile uint16_t*)
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((uintptr_t)sc->bar[BAR0].base_addr + offset)));
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
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(unsigned long)offset, val);
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return val;
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}
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static inline uint32_t
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bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
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{
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uint32_t val;
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#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
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if ((offset % 4) != 0)
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PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx",
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(unsigned long)offset);
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#endif
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val = (uint32_t)(*((volatile uint32_t*)
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((uintptr_t)sc->bar[BAR0].base_addr + offset)));
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
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(unsigned long)offset, val);
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return val;
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}
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#define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
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@ -1,96 +0,0 @@
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/*-
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* Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
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*
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* Eric Davis <edavis@broadcom.com>
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* David Christensen <davidch@broadcom.com>
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* Gary Zambrano <zambrano@broadcom.com>
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*
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* Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
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* Copyright (c) 2015 QLogic Corporation.
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* All rights reserved.
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* www.qlogic.com
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*
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* See LICENSE.bnx2x_pmd for copyright and licensing details.
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*/
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#include "bnx2x.h"
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/*
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* Debug versions of the 8/16/32 bit OS register read/write functions to
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* capture/display values read/written from/to the controller.
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*/
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void
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bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
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{
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val);
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*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
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}
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void
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bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
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{
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if ((offset % 2) != 0) {
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PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx",
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(unsigned long)offset);
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}
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x", (unsigned long)offset, val);
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*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
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}
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void
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bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
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{
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if ((offset % 4) != 0) {
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PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx",
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(unsigned long)offset);
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}
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val);
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*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
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}
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uint8_t
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bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
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{
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uint8_t val;
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val = (uint8_t)(*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)));
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val);
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return val;
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}
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uint16_t
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bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
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{
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uint16_t val;
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if ((offset % 2) != 0) {
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PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx",
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(unsigned long)offset);
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}
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val = (uint16_t)(*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)));
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val);
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return val;
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}
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uint32_t
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bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
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{
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uint32_t val;
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if ((offset % 4) != 0) {
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PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx",
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(unsigned long)offset);
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return 0;
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}
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val = (uint32_t)(*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)));
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PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val);
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return val;
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}
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