dma/hisilicon: support registers dump for Kunpeng 930
This patch supports dump Kunpeng930 DMA registers. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
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2265601837
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dd69081182
@ -460,29 +460,13 @@ hisi_dma_stats_reset(struct rte_dma_dev *dev, uint16_t vchan)
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}
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static void
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hisi_dma_get_dump_range(struct hisi_dma_dev *hw, uint32_t *start, uint32_t *end)
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{
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if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) {
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*start = HISI_DMA_HIP08_DUMP_START_REG;
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*end = HISI_DMA_HIP08_DUMP_END_REG;
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} else {
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*start = 0;
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*end = 0;
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}
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}
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static void
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hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
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hisi_dma_dump_range(struct hisi_dma_dev *hw, FILE *f, uint32_t start,
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uint32_t end)
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{
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#define DUMP_REGNUM_PER_LINE 4
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uint32_t start, end;
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uint32_t cnt, i;
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hisi_dma_get_dump_range(hw, &start, &end);
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(void)fprintf(f, " common-register:\n");
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cnt = 0;
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for (i = start; i <= end; i += sizeof(uint32_t)) {
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if (cnt % DUMP_REGNUM_PER_LINE == 0)
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@ -496,6 +480,40 @@ hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
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(void)fprintf(f, "\n");
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}
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static void
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hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
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{
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struct {
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uint8_t reg_layout;
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uint32_t start;
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uint32_t end;
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} reg_info[] = {
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{ HISI_DMA_REG_LAYOUT_HIP08,
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HISI_DMA_HIP08_DUMP_START_REG,
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HISI_DMA_HIP08_DUMP_END_REG },
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{ HISI_DMA_REG_LAYOUT_HIP09,
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HISI_DMA_HIP09_DUMP_REGION_A_START_REG,
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HISI_DMA_HIP09_DUMP_REGION_A_END_REG },
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{ HISI_DMA_REG_LAYOUT_HIP09,
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HISI_DMA_HIP09_DUMP_REGION_B_START_REG,
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HISI_DMA_HIP09_DUMP_REGION_B_END_REG },
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{ HISI_DMA_REG_LAYOUT_HIP09,
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HISI_DMA_HIP09_DUMP_REGION_C_START_REG,
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HISI_DMA_HIP09_DUMP_REGION_C_END_REG },
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{ HISI_DMA_REG_LAYOUT_HIP09,
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HISI_DMA_HIP09_DUMP_REGION_D_START_REG,
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HISI_DMA_HIP09_DUMP_REGION_D_END_REG },
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};
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uint32_t i;
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(void)fprintf(f, " common-register:\n");
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for (i = 0; i < RTE_DIM(reg_info); i++) {
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if (hw->reg_layout != reg_info[i].reg_layout)
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continue;
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hisi_dma_dump_range(hw, f, reg_info[i].start, reg_info[i].end);
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}
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}
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static void
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hisi_dma_dump_read_queue(struct hisi_dma_dev *hw, uint32_t qoff,
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char *buffer, int max_sz)
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@ -121,6 +121,14 @@ enum {
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#define HISI_DMA_HIP09_QUEUE_CFG_REG(queue_id) (0x800 + \
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(queue_id) * 0x20)
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#define HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B 16
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#define HISI_DMA_HIP09_DUMP_REGION_A_START_REG 0x0
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#define HISI_DMA_HIP09_DUMP_REGION_A_END_REG 0x368
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#define HISI_DMA_HIP09_DUMP_REGION_B_START_REG 0x800
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#define HISI_DMA_HIP09_DUMP_REGION_B_END_REG 0xA08
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#define HISI_DMA_HIP09_DUMP_REGION_C_START_REG 0x1800
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#define HISI_DMA_HIP09_DUMP_REGION_C_END_REG 0x1A4C
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#define HISI_DMA_HIP09_DUMP_REGION_D_START_REG 0x1C00
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#define HISI_DMA_HIP09_DUMP_REGION_D_END_REG 0x1CC4
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/**
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* In fact, there are multiple states, but it need to pay attention to
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