net/bnxt: handle reset notify async event from FW
When the FW upgrade is initiated the current instance of FW issues a HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY async notification to the driver. On receiving this notification, the PMD shall quiesce itself and poll on the HWRM_VER_GET FW command at regular intervals. Once the VER_GET command succeeds, the driver should go through the rediscovery process and re-initialize the device. Also register with FW for the reset notify async event. Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
This commit is contained in:
Kalesh AP
Ferruh Yigit
parent
1bf01f5135
commit
df6cd7c1f7
@ -333,6 +333,16 @@ struct bnxt_ctx_mem_info {
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struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
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};
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/* Maximum Firmware Reset bail out value in milliseconds */
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#define BNXT_MAX_FW_RESET_TIMEOUT 6000
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/* Minimum time required for the firmware readiness in milliseconds */
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#define BNXT_MIN_FW_READY_TIMEOUT 2000
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/* Frequency for the firmware readiness check in milliseconds */
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#define BNXT_FW_READY_WAIT_INTERVAL 100
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#define US_PER_MS 1000
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#define NS_PER_US 1000
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#define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
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struct bnxt {
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void *bar0;
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@ -463,6 +473,9 @@ struct bnxt {
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struct bnxt_ptp_cfg *ptp_cfg;
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uint16_t vf_resv_strategy;
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struct bnxt_ctx_mem_info *ctx;
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uint16_t fw_reset_min_msecs;
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uint16_t fw_reset_max_msecs;
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};
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int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
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@ -4,6 +4,7 @@
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*/
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#include <rte_malloc.h>
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#include <rte_alarm.h>
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#include "bnxt.h"
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#include "bnxt_cpr.h"
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@ -40,6 +41,21 @@ void bnxt_handle_async_event(struct bnxt *bp,
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case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED:
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PMD_DRV_LOG(INFO, "Port conn async event\n");
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break;
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case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY:
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/* timestamp_lo/hi values are in units of 100ms */
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bp->fw_reset_max_msecs = async_cmp->timestamp_hi ?
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rte_le_to_cpu_16(async_cmp->timestamp_hi) * 100 :
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BNXT_MAX_FW_RESET_TIMEOUT;
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bp->fw_reset_min_msecs = async_cmp->timestamp_lo ?
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async_cmp->timestamp_lo * 100 :
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BNXT_MIN_FW_READY_TIMEOUT;
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PMD_DRV_LOG(INFO,
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"Firmware non-fatal reset event received\n");
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bp->flags |= BNXT_FLAG_FW_RESET;
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rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
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(void *)bp);
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break;
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default:
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PMD_DRV_LOG(INFO, "handle_async_event id = 0x%x\n", event_id);
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break;
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@ -106,5 +106,6 @@ struct bnxt;
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void bnxt_handle_async_event(struct bnxt *bp, struct cmpl_base *cmp);
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void bnxt_handle_fwd_req(struct bnxt *bp, struct cmpl_base *cmp);
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int bnxt_event_hwrm_resp_handler(struct bnxt *bp, struct cmpl_base *cmp);
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void bnxt_dev_reset_and_resume(void *arg);
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#endif
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@ -11,6 +11,7 @@
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#include <rte_ethdev_pci.h>
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#include <rte_malloc.h>
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#include <rte_cycles.h>
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#include <rte_alarm.h>
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#include "bnxt.h"
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#include "bnxt_cpr.h"
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@ -166,6 +167,8 @@ static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
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static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
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static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
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static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
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static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
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static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
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int is_bnxt_in_error(struct bnxt *bp)
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{
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@ -201,19 +204,25 @@ static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
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return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
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}
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static void bnxt_free_mem(struct bnxt *bp)
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static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
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{
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bnxt_free_filter_mem(bp);
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bnxt_free_vnic_attributes(bp);
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bnxt_free_vnic_mem(bp);
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bnxt_free_stats(bp);
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bnxt_free_tx_rings(bp);
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bnxt_free_rx_rings(bp);
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/* tx/rx rings are configured as part of *_queue_setup callbacks.
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* If the number of rings change across fw update,
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* we don't have much choice except to warn the user.
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*/
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if (!reconfig) {
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bnxt_free_stats(bp);
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bnxt_free_tx_rings(bp);
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bnxt_free_rx_rings(bp);
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}
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bnxt_free_async_cp_ring(bp);
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}
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static int bnxt_alloc_mem(struct bnxt *bp)
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static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
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{
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int rc;
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@ -244,7 +253,7 @@ static int bnxt_alloc_mem(struct bnxt *bp)
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return 0;
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alloc_mem_err:
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bnxt_free_mem(bp);
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bnxt_free_mem(bp, reconfig);
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return rc;
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}
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@ -3523,6 +3532,89 @@ static const struct eth_dev_ops bnxt_dev_ops = {
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.timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
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};
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static void bnxt_dev_cleanup(struct bnxt *bp)
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{
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bnxt_set_hwrm_link_config(bp, false);
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bp->link_info.link_up = 0;
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if (bp->dev_stopped == 0)
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bnxt_dev_stop_op(bp->eth_dev);
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bnxt_uninit_resources(bp, true);
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}
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static int bnxt_restore_filters(struct bnxt *bp)
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{
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struct rte_eth_dev *dev = bp->eth_dev;
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int ret = 0;
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if (dev->data->all_multicast)
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ret = bnxt_allmulticast_enable_op(dev);
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if (dev->data->promiscuous)
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ret = bnxt_promiscuous_enable_op(dev);
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/* TODO restore other filters as well */
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return ret;
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}
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static void bnxt_dev_recover(void *arg)
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{
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struct bnxt *bp = arg;
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int timeout = bp->fw_reset_max_msecs;
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int rc = 0;
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do {
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rc = bnxt_hwrm_ver_get(bp);
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if (rc == 0)
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break;
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rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
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timeout -= BNXT_FW_READY_WAIT_INTERVAL;
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} while (rc && timeout);
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if (rc) {
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PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
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goto err;
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}
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rc = bnxt_init_resources(bp, true);
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if (rc) {
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PMD_DRV_LOG(ERR,
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"Failed to initialize resources after reset\n");
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goto err;
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}
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/* clear reset flag as the device is initialized now */
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bp->flags &= ~BNXT_FLAG_FW_RESET;
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rc = bnxt_dev_start_op(bp->eth_dev);
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if (rc) {
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PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
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goto err;
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}
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rc = bnxt_restore_filters(bp);
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if (rc)
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goto err;
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PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
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return;
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err:
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bp->flags |= BNXT_FLAG_FATAL_ERROR;
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bnxt_uninit_resources(bp, false);
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PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
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}
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void bnxt_dev_reset_and_resume(void *arg)
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{
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struct bnxt *bp = arg;
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int rc;
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bnxt_dev_cleanup(bp);
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rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
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bnxt_dev_recover, (void *)bp);
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if (rc)
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PMD_DRV_LOG(ERR, "Error setting recovery alarm");
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}
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static bool bnxt_vf_pciid(uint16_t id)
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{
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if (id == BROADCOM_DEV_ID_57304_VF ||
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@ -3965,6 +4057,22 @@ static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
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return rc;
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}
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static int bnxt_restore_dflt_mac(struct bnxt *bp)
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{
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int rc = 0;
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/* MAC is already configured in FW */
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if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
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return 0;
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/* Restore the old MAC configured */
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rc = bnxt_hwrm_set_mac(bp);
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if (rc)
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PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
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return rc;
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}
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static void bnxt_config_vf_req_fwd(struct bnxt *bp)
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{
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if (!BNXT_PF(bp))
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@ -4038,7 +4146,7 @@ static int bnxt_init_fw(struct bnxt *bp)
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return 0;
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}
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static int bnxt_init_resources(struct bnxt *bp)
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static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
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{
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int rc;
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@ -4046,9 +4154,15 @@ static int bnxt_init_resources(struct bnxt *bp)
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if (rc)
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return rc;
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rc = bnxt_setup_mac_addr(bp->eth_dev);
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if (rc)
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return rc;
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if (!reconfig_dev) {
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rc = bnxt_setup_mac_addr(bp->eth_dev);
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if (rc)
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return rc;
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} else {
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rc = bnxt_restore_dflt_mac(bp);
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if (rc)
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return rc;
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}
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bnxt_config_vf_req_fwd(bp);
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@ -4075,7 +4189,7 @@ static int bnxt_init_resources(struct bnxt *bp)
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}
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}
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rc = bnxt_alloc_mem(bp);
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rc = bnxt_alloc_mem(bp, reconfig_dev);
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if (rc)
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return rc;
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@ -4149,7 +4263,7 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev)
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"Failed to allocate hwrm resource rc: %x\n", rc);
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goto error_free;
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}
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rc = bnxt_init_resources(bp);
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rc = bnxt_init_resources(bp, false);
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if (rc)
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goto error_free;
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@ -4170,18 +4284,19 @@ error_free:
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}
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static int
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bnxt_uninit_resources(struct bnxt *bp)
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bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
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{
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int rc;
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bnxt_disable_int(bp);
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bnxt_free_int(bp);
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bnxt_free_mem(bp);
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bnxt_free_mem(bp, reconfig_dev);
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bnxt_hwrm_func_buf_unrgtr(bp);
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rc = bnxt_hwrm_func_driver_unregister(bp, 0);
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bp->flags &= ~BNXT_FLAG_REGISTERED;
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bnxt_free_ctx_mem(bp);
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bnxt_free_hwrm_resources(bp);
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if (!reconfig_dev)
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bnxt_free_hwrm_resources(bp);
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return rc;
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}
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@ -4197,7 +4312,7 @@ bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
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PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
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rc = bnxt_uninit_resources(bp);
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rc = bnxt_uninit_resources(bp, false);
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if (bp->grp_info != NULL) {
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rte_free(bp->grp_info);
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@ -27,6 +27,7 @@
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#include <rte_io.h>
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#define HWRM_CMD_TIMEOUT 6000000
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#define HWRM_SHORT_CMD_TIMEOUT 50000
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#define HWRM_SPEC_CODE_1_8_3 0x10803
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#define HWRM_VERSION_1_9_1 0x10901
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#define HWRM_VERSION_1_9_2 0x10903
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@ -97,6 +98,17 @@ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
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GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
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uint16_t mb_trigger_offset = use_kong_mb ?
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GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
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uint32_t timeout;
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/* Do not send HWRM commands to firmware in error state */
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if (bp->flags & BNXT_FLAG_FATAL_ERROR)
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return 0;
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/* For VER_GET command, set timeout as 50ms */
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if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
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timeout = HWRM_SHORT_CMD_TIMEOUT;
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else
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timeout = HWRM_CMD_TIMEOUT;
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if (bp->flags & BNXT_FLAG_SHORT_CMD ||
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msg_len > bp->max_req_len) {
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@ -139,7 +151,7 @@ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
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rte_write32(1, bar);
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/* Poll for the valid bit */
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for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
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for (i = 0; i < timeout; i++) {
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/* Sanity check on the resp->resp_len */
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rte_rmb();
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if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
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@ -151,7 +163,12 @@ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
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rte_delay_us(1);
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}
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if (i >= HWRM_CMD_TIMEOUT) {
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if (i >= timeout) {
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/* Suppress VER_GET timeout messages during reset recovery */
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if (bp->flags & BNXT_FLAG_FW_RESET &&
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rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
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return -ETIMEDOUT;
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PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
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req->req_type);
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return -ETIMEDOUT;
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@ -657,12 +674,21 @@ int bnxt_hwrm_func_reset(struct bnxt *bp)
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int bnxt_hwrm_func_driver_register(struct bnxt *bp)
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{
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int rc;
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uint32_t flags = 0;
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struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
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struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
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if (bp->flags & BNXT_FLAG_REGISTERED)
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return 0;
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flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
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/* PFs and trusted VFs should indicate the support of the
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* Master capability on non Stingray platform
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*/
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if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
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flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
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HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
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req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
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HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
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@ -683,14 +709,16 @@ int bnxt_hwrm_func_driver_register(struct bnxt *bp)
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* this HWRM sniffer list in FW because DPDK PF driver does
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* not support this.
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*/
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req.flags =
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rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
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flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
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}
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req.flags = rte_cpu_to_le_32(flags);
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req.async_event_fwd[0] |=
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rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
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ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
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ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
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ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
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ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
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req.async_event_fwd[1] |=
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rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
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ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
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@ -837,7 +865,10 @@ int bnxt_hwrm_ver_get(struct bnxt *bp)
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rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
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HWRM_CHECK_RESULT();
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if (bp->flags & BNXT_FLAG_FW_RESET)
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HWRM_CHECK_RESULT_SILENT();
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else
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||||
HWRM_CHECK_RESULT();
|
||||
|
||||
PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
|
||||
resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
|
||||
@ -2685,6 +2716,10 @@ int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
|
||||
if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
|
||||
bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
|
||||
PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
|
||||
} else if (BNXT_VF(bp) &&
|
||||
!(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
|
||||
bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
|
||||
PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
|
||||
}
|
||||
|
||||
if (mtu)
|
||||
|
||||
@ -21,6 +21,8 @@ struct bnxt_cp_ring_info;
|
||||
(1 << HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED)
|
||||
#define ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
|
||||
(1 << HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE)
|
||||
#define ASYNC_CMPL_EVENT_ID_RESET_NOTIFY \
|
||||
(1 << HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY)
|
||||
#define ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
|
||||
(1 << (HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD - 32))
|
||||
#define ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE \
|
||||
|
||||
@ -8918,6 +8918,17 @@ struct hwrm_func_drv_rgtr_input {
|
||||
*/
|
||||
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
|
||||
UINT32_C(0x20)
|
||||
/*
|
||||
* When this bit is 1, the function is indicating the support of the
|
||||
* Master capability. The Firmware will use this capability to select
|
||||
* the Master function. The master function will be used to initiate
|
||||
* designated functionality like error recovery etc. If none of the
|
||||
* registered PFs or trusted VFs indicate this support, then
|
||||
* firmware will select the 1st registered PF as Master capable
|
||||
* instance.
|
||||
*/
|
||||
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
|
||||
UINT32_C(0x40)
|
||||
uint32_t enables;
|
||||
/*
|
||||
* This bit must be '1' for the os_type field to be
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user