bus/pci: query PCI extended capabilities
By adding generic API, this patch removes individual functions/defines implemented by drivers to find extended PCI capabilities. Signed-off-by: Manish Chopra <manishc@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Reviewed-by: Gaetan Rivet <grive@u256.net> Reviewed-by: Jerin Jacob <jerinj@marvell.com>
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@ -705,6 +705,49 @@ rte_pci_get_iommu_class(void)
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return iova_mode;
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}
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off_t
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rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap)
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{
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off_t offset = RTE_PCI_CFG_SPACE_SIZE;
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uint32_t header;
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int ttl;
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/* minimum 8 bytes per capability */
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ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
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if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
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RTE_LOG(ERR, EAL, "error in reading extended capabilities\n");
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return -1;
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}
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/*
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* If we have no capabilities, this is indicated by cap ID,
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* cap version and next pointer all being 0.
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*/
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if (header == 0)
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return 0;
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while (ttl != 0) {
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if (RTE_PCI_EXT_CAP_ID(header) == cap)
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return offset;
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offset = RTE_PCI_EXT_CAP_NEXT(header);
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if (offset < RTE_PCI_CFG_SPACE_SIZE)
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break;
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if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
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RTE_LOG(ERR, EAL,
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"error in reading extended capabilities\n");
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return -1;
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}
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ttl--;
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}
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return 0;
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}
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struct rte_pci_bus rte_pci_bus = {
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.bus = {
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.scan = rte_pci_scan,
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@ -233,6 +233,25 @@ void rte_pci_unmap_device(struct rte_pci_device *dev);
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*/
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void rte_pci_dump(FILE *f);
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/**
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* Find device's extended PCI capability.
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*
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* @param dev
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* A pointer to rte_pci_device structure.
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*
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* @param cap
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* Extended capability to be found, which can be any from
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* RTE_PCI_EXT_CAP_ID_*, defined in librte_pci.
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*
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* @return
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* > 0: The offset of the next matching extended capability structure
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* within the device's PCI configuration space.
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* < 0: An error in PCI config space read.
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* = 0: Device does not support it.
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*/
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__rte_experimental
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off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
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/**
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* Register a PCI driver.
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*
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@ -16,3 +16,9 @@ DPDK_21 {
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local: *;
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};
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EXPERIMENTAL {
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global:
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rte_pci_find_ext_capability;
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};
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@ -1753,53 +1753,6 @@ ice_pf_setup(struct ice_pf *pf)
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return 0;
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}
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/* PCIe configuration space setting */
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#define PCI_CFG_SPACE_SIZE 256
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#define PCI_CFG_SPACE_EXP_SIZE 4096
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#define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
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#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
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#define PCI_EXT_CAP_ID_DSN 0x03
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static int
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ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
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{
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uint32_t header;
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int ttl;
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int pos = PCI_CFG_SPACE_SIZE;
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/* minimum 8 bytes per capability */
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ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
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if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
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PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
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return -1;
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}
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/*
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* If we have no capabilities, this is indicated by cap ID,
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* cap version and next pointer all being 0.
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*/
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if (header == 0)
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return 0;
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while (ttl-- > 0) {
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if (PCI_EXT_CAP_ID(header) == cap)
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return pos;
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pos = PCI_EXT_CAP_NEXT(header);
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if (pos < PCI_CFG_SPACE_SIZE)
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break;
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if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
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PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
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return -1;
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}
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}
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return 0;
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}
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/*
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* Extract device serial number from PCIe Configuration Space and
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* determine the pkg file path according to the DSN.
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@ -1807,12 +1760,12 @@ ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
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static int
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ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
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{
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int pos;
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off_t pos;
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char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
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uint32_t dsn_low, dsn_high;
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memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
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pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
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pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
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if (pos) {
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rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
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@ -746,59 +746,15 @@ nfp6000_set_interface(struct rte_pci_device *dev, struct nfp_cpp *cpp)
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return 0;
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}
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#define PCI_CFG_SPACE_SIZE 256
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#define PCI_CFG_SPACE_EXP_SIZE 4096
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#define PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff)
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#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
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#define PCI_EXT_CAP_ID_DSN 0x03
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static int
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nfp_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
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{
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uint32_t header;
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int ttl;
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int pos = PCI_CFG_SPACE_SIZE;
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/* minimum 8 bytes per capability */
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ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
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if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
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printf("nfp error reading extended capabilities\n");
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return -1;
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}
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/*
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* If we have no capabilities, this is indicated by cap ID,
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* cap version and next pointer all being 0.
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*/
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if (header == 0)
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return 0;
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while (ttl-- > 0) {
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if (PCI_EXT_CAP_ID(header) == cap)
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return pos;
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pos = PCI_EXT_CAP_NEXT(header);
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if (pos < PCI_CFG_SPACE_SIZE)
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break;
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if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
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printf("nfp error reading extended capabilities\n");
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return -1;
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}
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}
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return 0;
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}
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static int
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nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp)
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{
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uint16_t tmp;
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uint8_t serial[6];
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int serial_len = 6;
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int pos;
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off_t pos;
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pos = nfp_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
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pos = rte_pci_find_ext_capability(dev, RTE_PCI_EXT_CAP_ID_DSN);
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if (pos <= 0) {
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printf("PCI_EXT_CAP_ID_DSN not found. nfp set serial failed\n");
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return -1;
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@ -41,12 +41,6 @@
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#include "ifpga_rawdev.h"
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#include "ipn3ke_rawdev_api.h"
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#define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
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#define RTE_PCI_CFG_SPACE_SIZE 256
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#define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
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#define RTE_PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff)
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#define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
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#define PCI_VENDOR_ID_INTEL 0x8086
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/* PCI Device ID */
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#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
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@ -86,8 +80,8 @@ ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
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static int set_surprise_link_check_aer(
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struct ifpga_rawdev *ifpga_rdev, int force_disable);
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static int ifpga_pci_find_next_ext_capability(unsigned int fd,
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int start, int cap);
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static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
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int start, uint32_t cap);
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static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
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struct ifpga_rawdev *
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ifpga_rawdev_get(const struct rte_rawdev *rawdev)
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@ -144,8 +138,8 @@ ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
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return dev;
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}
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static int ifpga_pci_find_next_ext_capability(unsigned int fd,
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int start, int cap)
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static int
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ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
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{
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uint32_t header;
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int ttl;
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@ -183,7 +177,8 @@ int start, int cap)
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return 0;
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}
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static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
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static int
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ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
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{
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return ifpga_pci_find_next_ext_capability(fd, 0, cap);
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}
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@ -22,6 +22,21 @@ extern "C" {
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#include <inttypes.h>
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#include <sys/types.h>
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/*
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* Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
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* configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
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* configuration space.
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*/
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#define RTE_PCI_CFG_SPACE_SIZE 256
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#define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
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/* Extended Capabilities (PCI-X 2.0 and Express) */
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#define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
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#define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
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#define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
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#define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
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/** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */
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#define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
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#define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")
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