net/axgbe: support IEEE 1588 PTP
Add ethdev APIs to support PTP timestamping Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com> Acked-by: Amaranath Somalapuram <asomalap@amd.com>
This commit is contained in:
Selwin Sebastian
Ferruh Yigit
parent
0dd95bc917
commit
e04449488f
@ -46,6 +46,7 @@
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#endif
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#define AXGBE_HZ 250
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#define NSEC_PER_SEC 1000000000L
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/* DMA register offsets */
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#define DMA_MR 0x3000
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@ -492,6 +493,8 @@
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#define MAC_TSCR_TSEVNTENA_WIDTH 1
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#define MAC_TSCR_TSINIT_INDEX 2
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#define MAC_TSCR_TSINIT_WIDTH 1
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#define MAC_TSCR_TSUPDT_INDEX 3
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#define MAC_TSCR_TSUPDT_WIDTH 1
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#define MAC_TSCR_TSIPENA_INDEX 11
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#define MAC_TSCR_TSIPENA_WIDTH 1
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#define MAC_TSCR_TSIPV4ENA_INDEX 13
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@ -506,6 +509,8 @@
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#define MAC_TSCR_TXTSSTSM_WIDTH 1
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#define MAC_TSSR_TXTSC_INDEX 15
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#define MAC_TSSR_TXTSC_WIDTH 1
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#define MAC_STNUR_ADDSUB_INDEX 31
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#define MAC_STNUR_ADDSUB_WIDTH 1
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#define MAC_TXSNR_TXTSSTSMIS_INDEX 31
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#define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
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#define MAC_VLANHTR_VLHT_INDEX 0
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@ -539,6 +544,7 @@
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#define MAC_VR_USERVER_INDEX 16
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#define MAC_VR_USERVER_WIDTH 8
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/* MMC register offsets */
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#define MMC_CR 0x0800
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#define MMC_RISR 0x0804
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@ -1171,6 +1177,8 @@
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#define RX_CONTEXT_DESC3_TSA_WIDTH 1
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#define RX_CONTEXT_DESC3_TSD_INDEX 6
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#define RX_CONTEXT_DESC3_TSD_WIDTH 1
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#define RX_CONTEXT_DESC3_PMT_INDEX 0
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#define RX_CONTEXT_DESC3_PMT_WIDTH 4
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#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
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#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
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@ -8,6 +8,7 @@
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#include "axgbe_common.h"
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#include "axgbe_phy.h"
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#include "axgbe_regs.h"
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#include "rte_time.h"
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static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
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static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
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@ -85,6 +86,31 @@ static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
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const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
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static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
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static int
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axgbe_timesync_enable(struct rte_eth_dev *dev);
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static int
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axgbe_timesync_disable(struct rte_eth_dev *dev);
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static int
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axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp, uint32_t flags);
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static int
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axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp);
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static int
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axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
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static int
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axgbe_timesync_read_time(struct rte_eth_dev *dev,
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struct timespec *timestamp);
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static int
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axgbe_timesync_write_time(struct rte_eth_dev *dev,
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const struct timespec *timestamp);
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static void
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axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec,
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unsigned int nsec);
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static void
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axgbe_update_tstamp_addend(struct axgbe_port *pdata,
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unsigned int addend);
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struct axgbe_xstats {
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char name[RTE_ETH_XSTATS_NAME_SIZE];
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int offset;
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@ -225,6 +251,13 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
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.txq_info_get = axgbe_txq_info_get,
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.dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get,
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.mtu_set = axgb_mtu_set,
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.timesync_enable = axgbe_timesync_enable,
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.timesync_disable = axgbe_timesync_disable,
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.timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp,
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.timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp,
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.timesync_adjust_time = axgbe_timesync_adjust_time,
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.timesync_read_time = axgbe_timesync_read_time,
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.timesync_write_time = axgbe_timesync_write_time,
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};
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static int axgbe_phy_reset(struct axgbe_port *pdata)
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@ -1395,6 +1428,7 @@ axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
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return ptypes;
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return NULL;
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}
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static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
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{
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struct rte_eth_dev_info dev_info;
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@ -1424,6 +1458,310 @@ static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
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dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
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return 0;
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}
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static void
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axgbe_update_tstamp_time(struct axgbe_port *pdata,
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unsigned int sec, unsigned int nsec, int addsub)
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{
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unsigned int count = 100;
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uint32_t sub_val = 0;
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uint32_t sub_val_sec = 0xFFFFFFFF;
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uint32_t sub_val_nsec = 0x3B9ACA00;
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if (addsub) {
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if (sec)
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sub_val = sub_val_sec - (sec - 1);
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else
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sub_val = sec;
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AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val);
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sub_val = sub_val_nsec - nsec;
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AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val);
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AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1);
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} else {
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AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
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AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0);
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AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
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}
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AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
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/* Wait for time update to complete */
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while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
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rte_delay_ms(1);
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}
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static inline uint64_t
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div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)
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{
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*remainder = dividend % divisor;
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return dividend / divisor;
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}
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static inline uint64_t
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div_u64(uint64_t dividend, uint32_t divisor)
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{
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uint32_t remainder;
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return div_u64_rem(dividend, divisor, &remainder);
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}
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static int
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axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta)
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{
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uint64_t adjust;
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uint32_t addend, diff;
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unsigned int neg_adjust = 0;
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if (delta < 0) {
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neg_adjust = 1;
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delta = -delta;
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}
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adjust = (uint64_t)pdata->tstamp_addend;
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adjust *= delta;
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diff = (uint32_t)div_u64(adjust, 1000000000UL);
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addend = (neg_adjust) ? pdata->tstamp_addend - diff :
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pdata->tstamp_addend + diff;
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pdata->tstamp_addend = addend;
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axgbe_update_tstamp_addend(pdata, addend);
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return 0;
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}
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static int
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axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
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{
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struct axgbe_port *pdata = dev->data->dev_private;
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struct timespec timestamp_delta;
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axgbe_adjfreq(pdata, delta);
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pdata->systime_tc.nsec += delta;
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if (delta < 0) {
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delta = -delta;
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timestamp_delta = rte_ns_to_timespec(delta);
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axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
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timestamp_delta.tv_nsec, 1);
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} else {
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timestamp_delta = rte_ns_to_timespec(delta);
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axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
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timestamp_delta.tv_nsec, 0);
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}
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return 0;
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}
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static int
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axgbe_timesync_read_time(struct rte_eth_dev *dev,
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struct timespec *timestamp)
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{
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uint64_t nsec;
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struct axgbe_port *pdata = dev->data->dev_private;
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nsec = AXGMAC_IOREAD(pdata, MAC_STSR);
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nsec *= NSEC_PER_SEC;
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nsec += AXGMAC_IOREAD(pdata, MAC_STNR);
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*timestamp = rte_ns_to_timespec(nsec);
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return 0;
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}
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static int
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axgbe_timesync_write_time(struct rte_eth_dev *dev,
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const struct timespec *timestamp)
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{
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unsigned int count = 100;
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struct axgbe_port *pdata = dev->data->dev_private;
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AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec);
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AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec);
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AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
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/* Wait for time update to complete */
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while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
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rte_delay_ms(1);
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if (!count)
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PMD_DRV_LOG(ERR, "Timed out update timestamp\n");
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return 0;
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}
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static void
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axgbe_update_tstamp_addend(struct axgbe_port *pdata,
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uint32_t addend)
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{
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unsigned int count = 100;
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AXGMAC_IOWRITE(pdata, MAC_TSAR, addend);
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AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
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/* Wait for addend update to complete */
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while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
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rte_delay_ms(1);
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if (!count)
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PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n");
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}
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static void
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axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec,
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unsigned int nsec)
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{
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unsigned int count = 100;
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/*System Time Sec Update*/
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AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
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/*System Time nanoSec Update*/
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AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
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/*Initialize Timestamp*/
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AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
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/* Wait for time update to complete */
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while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
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rte_delay_ms(1);
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if (!count)
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PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n");
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}
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static int
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axgbe_timesync_enable(struct rte_eth_dev *dev)
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{
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struct axgbe_port *pdata = dev->data->dev_private;
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unsigned int mac_tscr = 0;
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uint64_t dividend;
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struct timespec timestamp;
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uint64_t nsec;
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/* Set one nano-second accuracy */
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
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/* Set fine timestamp update */
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
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/* Overwrite earlier timestamps */
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
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AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
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/* Enabling processing of ptp over eth pkt */
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
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/* Enable timestamp for all pkts*/
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
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/* enabling timestamp */
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
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AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
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/* Exit if timestamping is not enabled */
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if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) {
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PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n");
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return 0;
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}
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/* Sub-second Increment Value*/
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AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC);
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/* Sub-nanosecond Increment Value */
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AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC);
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pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
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dividend = 50000000;
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dividend <<= 32;
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pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate);
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axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
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axgbe_set_tstamp_time(pdata, 0, 0);
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/* Initialize the timecounter */
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memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter));
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pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK;
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pdata->systime_tc.cc_shift = 0;
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pdata->systime_tc.nsec_mask = 0;
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PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n");
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/* Updating the counter once with clock real time */
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clock_gettime(CLOCK_REALTIME, ×tamp);
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nsec = rte_timespec_to_ns(×tamp);
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nsec = rte_timecounter_update(&pdata->systime_tc, nsec);
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axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec);
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return 0;
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}
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static int
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axgbe_timesync_disable(struct rte_eth_dev *dev)
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{
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struct axgbe_port *pdata = dev->data->dev_private;
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unsigned int mac_tscr = 0;
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/*disable timestamp for all pkts*/
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0);
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/*disable the addened register*/
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AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0);
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/* disable timestamp update */
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0);
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/*disable time stamp*/
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AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0);
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return 0;
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}
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static int
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axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp, uint32_t flags)
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{
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uint64_t nsec = 0;
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volatile union axgbe_rx_desc *desc;
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uint16_t idx, pmt;
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struct axgbe_rx_queue *rxq = *dev->data->rx_queues;
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idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
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desc = &rxq->desc[idx];
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while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
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rte_delay_ms(1);
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if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) {
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if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) &&
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!AXGMAC_GET_BITS_LE(desc->write.desc3,
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RX_CONTEXT_DESC3, TSD)) {
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pmt = AXGMAC_GET_BITS_LE(desc->write.desc3,
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RX_CONTEXT_DESC3, PMT);
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nsec = rte_le_to_cpu_32(desc->write.desc1);
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nsec *= NSEC_PER_SEC;
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nsec += rte_le_to_cpu_32(desc->write.desc0);
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if (nsec != 0xffffffffffffffffULL) {
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if (pmt == 0x01)
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*timestamp = rte_ns_to_timespec(nsec);
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PMD_DRV_LOG(DEBUG,
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"flags = 0x%x nsec = %"PRIu64"\n",
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flags, nsec);
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}
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}
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}
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return 0;
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}
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static int
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axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp)
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{
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uint64_t nsec;
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struct axgbe_port *pdata = dev->data->dev_private;
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unsigned int tx_snr, tx_ssr;
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rte_delay_us(5);
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if (pdata->vdata->tx_tstamp_workaround) {
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tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
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tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
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} else {
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tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
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tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
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}
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if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) {
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PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n");
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return 0;
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}
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nsec = tx_ssr;
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nsec *= NSEC_PER_SEC;
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nsec += tx_snr;
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PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n",
|
||||
nsec, tx_ssr, tx_snr);
|
||||
*timestamp = rte_ns_to_timespec(nsec);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
|
||||
{
|
||||
unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
#include <rte_mempool.h>
|
||||
#include <rte_lcore.h>
|
||||
#include "axgbe_common.h"
|
||||
#include "rte_time.h"
|
||||
|
||||
#define IRQ 0xff
|
||||
#define VLAN_HLEN 4
|
||||
@ -63,6 +64,13 @@
|
||||
#define AXGBE_V2_DMA_CLOCK_FREQ 500000000
|
||||
#define AXGBE_V2_PTP_CLOCK_FREQ 125000000
|
||||
|
||||
/* Timestamp support - values based on 50MHz PTP clock
|
||||
* 50MHz => 20 nsec
|
||||
*/
|
||||
#define AXGBE_TSTAMP_SSINC 20
|
||||
#define AXGBE_TSTAMP_SNSINC 0
|
||||
#define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
|
||||
|
||||
#define AXGMAC_FIFO_MIN_ALLOC 2048
|
||||
#define AXGMAC_FIFO_UNIT 256
|
||||
#define AXGMAC_FIFO_ALIGN(_x) \
|
||||
@ -645,6 +653,12 @@ struct axgbe_port {
|
||||
unsigned int hash_table_count;
|
||||
unsigned int uc_hash_mac_addr;
|
||||
unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE];
|
||||
|
||||
/* For IEEE1588 PTP */
|
||||
struct rte_timecounter systime_tc;
|
||||
struct rte_timecounter tx_tstamp;
|
||||
unsigned int tstamp_addend;
|
||||
|
||||
};
|
||||
|
||||
void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
|
||||
|
||||
@ -275,6 +275,10 @@ axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
|
||||
/* Get the RSS hash */
|
||||
if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
|
||||
mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
|
||||
/* Indicate if a Context Descriptor is next */
|
||||
if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CDA))
|
||||
mbuf->ol_flags |= PKT_RX_IEEE1588_PTP
|
||||
| PKT_RX_IEEE1588_TMST;
|
||||
pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3,
|
||||
PL) - rxq->crc_len;
|
||||
/* Mbuf populate */
|
||||
@ -722,6 +726,10 @@ static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,
|
||||
/* Total msg length to transmit */
|
||||
AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,
|
||||
mbuf->pkt_len);
|
||||
/* Timestamp enablement check */
|
||||
if (mbuf->ol_flags & PKT_TX_IEEE1588_TMST)
|
||||
AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1);
|
||||
rte_wmb();
|
||||
/* Mark it as First and Last Descriptor */
|
||||
AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);
|
||||
AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
|
||||
/* Useful to avoid shifting for every descriptor prepration*/
|
||||
#define TX_DESC_CTRL_FLAGS 0xb000000000000000
|
||||
#define TX_DESC_CTRL_FLAG_TMST 0x40000000
|
||||
#define TX_FREE_BULK 8
|
||||
#define TX_FREE_BULK_CHECK (TX_FREE_BULK - 1)
|
||||
|
||||
@ -20,8 +21,13 @@ static inline void
|
||||
axgbe_vec_tx(volatile struct axgbe_tx_desc *desc,
|
||||
struct rte_mbuf *mbuf)
|
||||
{
|
||||
uint64_t tmst_en = 0;
|
||||
/* Timestamp enablement check */
|
||||
if (mbuf->ol_flags & PKT_TX_IEEE1588_TMST)
|
||||
tmst_en = TX_DESC_CTRL_FLAG_TMST;
|
||||
__m128i descriptor = _mm_set_epi64x((uint64_t)mbuf->pkt_len << 32 |
|
||||
TX_DESC_CTRL_FLAGS | mbuf->data_len,
|
||||
TX_DESC_CTRL_FLAGS | mbuf->data_len
|
||||
| tmst_en,
|
||||
mbuf->buf_iova
|
||||
+ mbuf->data_off);
|
||||
_mm_store_si128((__m128i *)desc, descriptor);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user