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e1000: minor changes

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Signed-off-by: Intel
This commit is contained in:
Intel 2012-12-20 00:00:00 +01:00 committed by Thomas Monjalon
parent 5e305acc2e
commit e094e8f954
3 changed files with 37 additions and 28 deletions
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10
lib/librte_pmd_e1000/e1000_logs.h
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@ -35,35 +35,35 @@
#ifndef _E1000_LOGS_H_ #ifndef _E1000_LOGS_H_
#define _E1000_LOGS_H_ #define _E1000_LOGS_H_
#ifdef RTE_LIBRTE_IGB_DEBUG_INIT #ifdef RTE_LIBRTE_E1000_DEBUG_INIT
#define PMD_INIT_LOG(level, fmt, args...) \ #define PMD_INIT_LOG(level, fmt, args...) \
RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args) RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
#else #else
#define PMD_INIT_LOG(level, fmt, args...) do { } while(0) #define PMD_INIT_LOG(level, fmt, args...) do { } while(0)
#endif #endif
#ifdef RTE_LIBRTE_IGB_DEBUG_RX #ifdef RTE_LIBRTE_E1000_DEBUG_RX
#define PMD_RX_LOG(level, fmt, args...) \ #define PMD_RX_LOG(level, fmt, args...) \
RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args) RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
#else #else
#define PMD_RX_LOG(level, fmt, args...) do { } while(0) #define PMD_RX_LOG(level, fmt, args...) do { } while(0)
#endif #endif
#ifdef RTE_LIBRTE_IGB_DEBUG_TX #ifdef RTE_LIBRTE_E1000_DEBUG_TX
#define PMD_TX_LOG(level, fmt, args...) \ #define PMD_TX_LOG(level, fmt, args...) \
RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args) RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
#else #else
#define PMD_TX_LOG(level, fmt, args...) do { } while(0) #define PMD_TX_LOG(level, fmt, args...) do { } while(0)
#endif #endif
#ifdef RTE_LIBRTE_IGB_DEBUG_TX_FREE #ifdef RTE_LIBRTE_E1000_DEBUG_TX_FREE
#define PMD_TX_FREE_LOG(level, fmt, args...) \ #define PMD_TX_FREE_LOG(level, fmt, args...) \
RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args) RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
#else #else
#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while(0) #define PMD_TX_FREE_LOG(level, fmt, args...) do { } while(0)
#endif #endif
#ifdef RTE_LIBRTE_IGB_DEBUG_DRIVER #ifdef RTE_LIBRTE_E1000_DEBUG_DRIVER
#define PMD_DRV_LOG(level, fmt, args...) \ #define PMD_DRV_LOG(level, fmt, args...) \
RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args) RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
#else #else

6
lib/librte_pmd_e1000/igb_ethdev.c
View File

@ -54,8 +54,7 @@
#include <rte_malloc.h> #include <rte_malloc.h>
#include "e1000_logs.h" #include "e1000_logs.h"
#include "igb/e1000_api.h" #include "e1000/e1000_api.h"
#include "igb/e1000_hw.h"
#include "e1000_ethdev.h" #include "e1000_ethdev.h"
static int eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q, static int eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q,
@ -96,7 +95,8 @@ static int eth_igb_led_off(struct rte_eth_dev *dev);
static void igb_intr_disable(struct e1000_hw *hw); static void igb_intr_disable(struct e1000_hw *hw);
static int igb_get_rx_buffer_size(struct e1000_hw *hw); static int igb_get_rx_buffer_size(struct e1000_hw *hw);
static void eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr, static void eth_igb_rar_set(struct rte_eth_dev *dev,
struct ether_addr *mac_addr,
uint32_t index, uint32_t pool); uint32_t index, uint32_t pool);
static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index); static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);

49
lib/librte_pmd_e1000/igb_rxtx.c
View File

@ -72,7 +72,7 @@
#include <rte_string_fns.h> #include <rte_string_fns.h>
#include "e1000_logs.h" #include "e1000_logs.h"
#include "igb/e1000_api.h" #include "e1000/e1000_api.h"
#include "e1000_ethdev.h" #include "e1000_ethdev.h"
static inline struct rte_mbuf * static inline struct rte_mbuf *
@ -139,7 +139,7 @@ struct igb_rx_queue {
enum igb_advctx_num { enum igb_advctx_num {
IGB_CTX_0 = 0, /**< CTX0 */ IGB_CTX_0 = 0, /**< CTX0 */
IGB_CTX_1 = 1, /**< CTX1 */ IGB_CTX_1 = 1, /**< CTX1 */
IGB_CTX_NUM = 2, /**< CTX NUM */ IGB_CTX_NUM = 2, /**< CTX_NUM */
}; };
/** /**
@ -148,7 +148,7 @@ enum igb_advctx_num {
struct igb_advctx_info { struct igb_advctx_info {
uint16_t flags; /**< ol_flags related to context build. */ uint16_t flags; /**< ol_flags related to context build. */
uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */ uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
uint32_t vlan_macip_lens; /**< vlan, mac.ip length. */ union rte_vlan_macip vlan_macip_lens; /**< vlan, mac & ip length. */
}; };
/** /**
@ -162,15 +162,19 @@ struct igb_tx_queue {
uint32_t txd_type; /**< Device-specific TXD type */ uint32_t txd_type; /**< Device-specific TXD type */
uint16_t nb_tx_desc; /**< number of TX descriptors. */ uint16_t nb_tx_desc; /**< number of TX descriptors. */
uint16_t tx_tail; /**< Current value of TDT register. */ uint16_t tx_tail; /**< Current value of TDT register. */
uint16_t tx_head; /**< Index of first used TX descriptor. */ uint16_t tx_head;
/**< Index of first used TX descriptor. */
uint16_t queue_id; /**< TX queue index. */ uint16_t queue_id; /**< TX queue index. */
uint8_t port_id; /**< Device port identifier. */ uint8_t port_id; /**< Device port identifier. */
uint8_t pthresh; /**< Prefetch threshold register. */ uint8_t pthresh; /**< Prefetch threshold register. */
uint8_t hthresh; /**< Host threshold register. */ uint8_t hthresh; /**< Host threshold register. */
uint8_t wthresh; /**< Write-back threshold register. */ uint8_t wthresh; /**< Write-back threshold register. */
uint32_t ctx_curr; /**< Current used hardware descriptor. */ uint32_t ctx_curr;
uint32_t ctx_start;/**< Start context position for transmit queue. */ /**< Current used hardware descriptor. */
struct igb_advctx_info ctx_cache[IGB_CTX_NUM]; /**< Hardware context history.*/ uint32_t ctx_start;
/**< Start context position for transmit queue. */
struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
/**< Hardware context history.*/
}; };
#if 1 #if 1
@ -255,7 +259,8 @@ igbe_set_xmit_ctx(struct igb_tx_queue* txq,
txq->ctx_cache[ctx_curr].flags = ol_flags; txq->ctx_cache[ctx_curr].flags = ol_flags;
txq->ctx_cache[ctx_curr].cmp_mask = cmp_mask; txq->ctx_cache[ctx_curr].cmp_mask = cmp_mask;
txq->ctx_cache[ctx_curr].vlan_macip_lens = vlan_macip_lens & cmp_mask; txq->ctx_cache[ctx_curr].vlan_macip_lens.data =
vlan_macip_lens & cmp_mask;
ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl); ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens); ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
@ -273,7 +278,7 @@ what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
{ {
/* If match with the current context */ /* If match with the current context */
if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) && if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
(txq->ctx_cache[txq->ctx_curr].vlan_macip_lens == (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
(txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) { (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
return txq->ctx_curr; return txq->ctx_curr;
} }
@ -281,7 +286,7 @@ what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
/* If match with the second context */ /* If match with the second context */
txq->ctx_curr ^= 1; txq->ctx_curr ^= 1;
if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) && if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
(txq->ctx_cache[txq->ctx_curr].vlan_macip_lens == (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
(txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) { (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
return txq->ctx_curr; return txq->ctx_curr;
} }
@ -356,12 +361,13 @@ eth_igb_xmit_pkts(struct igb_tx_queue *txq, struct rte_mbuf **tx_pkts,
tx_last = (uint16_t) (tx_id + tx_pkt->pkt.nb_segs - 1); tx_last = (uint16_t) (tx_id + tx_pkt->pkt.nb_segs - 1);
ol_flags = tx_pkt->ol_flags; ol_flags = tx_pkt->ol_flags;
vlan_macip_lens = (tx_pkt->pkt.vlan_tci << 16) | (tx_pkt->pkt.l2_len << E1000_ADVTXD_MACLEN_SHIFT) | tx_pkt->pkt.l3_len; vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
tx_ol_req = (ol_flags & PKT_TX_OFFLOAD_MASK); tx_ol_req = (ol_flags & PKT_TX_OFFLOAD_MASK);
/* If a Context Descriptor need be built . */ /* If a Context Descriptor need be built . */
if (tx_ol_req) { if (tx_ol_req) {
ctx = what_advctx_update(txq, tx_ol_req,vlan_macip_lens); ctx = what_advctx_update(txq, tx_ol_req,
vlan_macip_lens);
/* Only allocate context descriptor if required*/ /* Only allocate context descriptor if required*/
new_ctx = (ctx == IGB_CTX_NUM); new_ctx = (ctx == IGB_CTX_NUM);
ctx = txq->ctx_curr; ctx = txq->ctx_curr;
@ -736,7 +742,8 @@ eth_igb_recv_pkts(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss; rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data); hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
/* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */ /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
rxm->pkt.vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan); rxm->pkt.vlan_macip.f.vlan_tci =
rte_le_to_cpu_16(rxd.wb.upper.vlan);
pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss); pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
pkt_flags = (pkt_flags | pkt_flags = (pkt_flags |
@ -970,7 +977,8 @@ eth_igb_recv_scattered_pkts(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
* The vlan_tci field is only valid when PKT_RX_VLAN_PKT is * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
* set in the pkt_flags field. * set in the pkt_flags field.
*/ */
first_seg->pkt.vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan); first_seg->pkt.vlan_macip.f.vlan_tci =
rte_le_to_cpu_16(rxd.wb.upper.vlan);
hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data); hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss); pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
pkt_flags = (pkt_flags | rx_desc_status_to_pkt_flags(staterr)); pkt_flags = (pkt_flags | rx_desc_status_to_pkt_flags(staterr));
@ -1203,15 +1211,15 @@ eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
if (tx_conf->tx_free_thresh != 0) if (tx_conf->tx_free_thresh != 0)
RTE_LOG(WARNING, PMD, RTE_LOG(WARNING, PMD,
"The tx_free_thresh parameter is not " "The tx_free_thresh parameter is not "
"used for the 1G driver."); "used for the 1G driver.\n");
if (tx_conf->tx_rs_thresh != 0) if (tx_conf->tx_rs_thresh != 0)
RTE_LOG(WARNING, PMD, RTE_LOG(WARNING, PMD,
"The tx_rs_thresh parameter is not " "The tx_rs_thresh parameter is not "
"used for the 1G driver."); "used for the 1G driver.\n");
if (tx_conf->tx_thresh.wthresh == 0) if (tx_conf->tx_thresh.wthresh == 0)
RTE_LOG(WARNING, PMD, RTE_LOG(WARNING, PMD,
"To improve 1G driver performance, consider setting " "To improve 1G driver performance, consider setting "
"the TX WTHRESH value to 4, 8, or 16."); "the TX WTHRESH value to 4, 8, or 16.\n");
/* Free memory prior to re-allocation if needed */ /* Free memory prior to re-allocation if needed */
if (dev->data->tx_queues[queue_idx] != NULL) if (dev->data->tx_queues[queue_idx] != NULL)
@ -1763,19 +1771,20 @@ eth_igb_rx_init(struct rte_eth_dev *dev)
/* set STRCRC bit in all queues for Powerville */ /* set STRCRC bit in all queues for Powerville */
if (hw->mac.type == e1000_i350) { if (hw->mac.type == e1000_i350) {
for (i = 0; i < dev->data->nb_rx_queues; i++) { for (i = 0; i < dev->data->nb_rx_queues; i++) {
uint32_t dvmolr = E1000_READ_REG(hw, E1000_DVMOLR(i)); uint32_t dvmolr = E1000_READ_REG(hw,
E1000_DVMOLR(i));
dvmolr |= E1000_DVMOLR_STRCRC; dvmolr |= E1000_DVMOLR_STRCRC;
E1000_WRITE_REG(hw, E1000_DVMOLR(i), dvmolr); E1000_WRITE_REG(hw, E1000_DVMOLR(i), dvmolr);
} }
} }
} else { } else {
rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */ rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
/* clear STRCRC bit in all queues for Powerville */ /* clear STRCRC bit in all queues for Powerville */
if (hw->mac.type == e1000_i350) { if (hw->mac.type == e1000_i350) {
for (i = 0; i < dev->data->nb_rx_queues; i++) { for (i = 0; i < dev->data->nb_rx_queues; i++) {
uint32_t dvmolr = E1000_READ_REG(hw, E1000_DVMOLR(i)); uint32_t dvmolr = E1000_READ_REG(hw,
E1000_DVMOLR(i));
dvmolr &= ~E1000_DVMOLR_STRCRC; dvmolr &= ~E1000_DVMOLR_STRCRC;
E1000_WRITE_REG(hw, E1000_DVMOLR(i), dvmolr); E1000_WRITE_REG(hw, E1000_DVMOLR(i), dvmolr);
} }