ethdev: add support for device offload capabilities

1) Make device RX and TX offload capabilities to be returned in the
   rte_eth_dev_info data structure by the function rte_eth_dev_info_get

   The following initial set of RX offload capabilities are defined:
   - VLAN header stripping
   - IPv4 header checksum check
   - UDP checksum check
   - TCP checksum check
   - TCP large receive offload (LRO)

   The following initial set of TX offload capabilities are defined:
   - VLAN header insertion
   - IPv4 header checksum computation
   - UDP checksum computation
   - TCP checksum computation
   - SCTP checksum computation
   - TCP segmentation offload (Transmit Segmentation Offload)
   - UDP segmentation offload

   2) Update the eth_dev_infos_get() function of the igb and ixgbe PMDs
      to return the offload capabilities which are supported by the
      device and that are effectively managed by the driver.

Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Signed-off-by: Ivan Boule <ivan.boule@6wind.com>
This commit is contained in:
Ivan Boule 2013-04-16 14:42:33 +02:00 committed by Thomas Monjalon
parent 3297c8073b
commit e2b75e3551
4 changed files with 54 additions and 6 deletions

View File

@ -747,6 +747,9 @@ rte_eth_dev_info_get(uint8_t port_id, struct rte_eth_dev_info *dev_info)
}
dev = &rte_eth_devices[port_id];
/* Default device offload capabilities to zero */
dev_info->rx_offload_capa = 0;
dev_info->tx_offload_capa = 0;
FUNC_PTR_OR_RET(*dev->dev_ops->dev_infos_get);
(*dev->dev_ops->dev_infos_get)(dev, dev_info);
dev_info->pci_dev = dev->pci_dev;

View File

@ -534,14 +534,37 @@ struct rte_eth_conf {
* an Ethernet device, such as the controlling driver of the device,
* its PCI context, etc...
*/
/**
* RX offload capabilities of a device.
*/
#define DEV_RX_OFFLOAD_VLAN_STRIP 0x00000001
#define DEV_RX_OFFLOAD_IPV4_CKSUM 0x00000002
#define DEV_RX_OFFLOAD_UDP_CKSUM 0x00000004
#define DEV_RX_OFFLOAD_TCP_CKSUM 0x00000008
#define DEV_RX_OFFLOAD_TCP_LRO 0x00000010
/**
* TX offload capabilities of a device.
*/
#define DEV_TX_OFFLOAD_VLAN_INSERT 0x00000001
#define DEV_TX_OFFLOAD_IPV4_CKSUM 0x00000002
#define DEV_TX_OFFLOAD_UDP_CKSUM 0x00000004
#define DEV_TX_OFFLOAD_TCP_CKSUM 0x00000008
#define DEV_TX_OFFLOAD_SCTP_CKSUM 0x00000010
#define DEV_TX_OFFLOAD_TCP_TSO 0x00000020
#define DEV_TX_OFFLOAD_UDP_TSO 0x00000040
struct rte_eth_dev_info {
struct rte_pci_device *pci_dev; /**< Device PCI information. */
const char *driver_name; /**< Device Driver name. */
uint32_t min_rx_bufsize; /**< Minimum size of RX buffer. */
uint32_t max_rx_pktlen; /**< Maximum configurable length of RX pkt. */
uint16_t max_rx_queues; /**< Maximum number of RX queues. */
uint16_t max_tx_queues; /**< Maximum number of TX queues. */
uint32_t max_mac_addrs; /**< Maximum number of MAC addresses. */
const char *driver_name; /**< Device Driver name. */
uint32_t min_rx_bufsize; /**< Minimum size of RX buffer. */
uint32_t max_rx_pktlen; /**< Maximum configurable length of RX pkt. */
uint16_t max_rx_queues; /**< Maximum number of RX queues. */
uint16_t max_tx_queues; /**< Maximum number of TX queues. */
uint32_t max_mac_addrs; /**< Maximum number of MAC addresses. */
uint32_t rx_offload_capa; /**< Device RX offload capabilities. */
uint32_t tx_offload_capa; /**< Device TX offload capabilities. */
};
struct rte_eth_dev;

View File

@ -803,6 +803,17 @@ eth_igb_infos_get(struct rte_eth_dev *dev,
dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
dev_info->max_mac_addrs = hw->mac.rar_entry_count;
dev_info->rx_offload_capa =
DEV_RX_OFFLOAD_VLAN_STRIP |
DEV_RX_OFFLOAD_IPV4_CKSUM |
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM;
dev_info->tx_offload_capa =
DEV_TX_OFFLOAD_VLAN_INSERT |
DEV_TX_OFFLOAD_IPV4_CKSUM |
DEV_TX_OFFLOAD_UDP_CKSUM |
DEV_TX_OFFLOAD_TCP_CKSUM |
DEV_TX_OFFLOAD_SCTP_CKSUM;
switch (hw->mac.type) {
case e1000_82575:

View File

@ -1131,6 +1131,17 @@ ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
dev_info->max_mac_addrs = hw->mac.num_rar_entries;
dev_info->rx_offload_capa =
DEV_RX_OFFLOAD_VLAN_STRIP |
DEV_RX_OFFLOAD_IPV4_CKSUM |
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM;
dev_info->tx_offload_capa =
DEV_TX_OFFLOAD_VLAN_INSERT |
DEV_TX_OFFLOAD_IPV4_CKSUM |
DEV_TX_OFFLOAD_UDP_CKSUM |
DEV_TX_OFFLOAD_TCP_CKSUM |
DEV_TX_OFFLOAD_SCTP_CKSUM;
}
/* return 0 means link status changed, -1 means not changed */