regex/mlx5: support configuration
This commit implements the configure function. This function is responsible to configure the RegEx engine. Signed-off-by: Ori Kam <orika@mellanox.com>
This commit is contained in:
Ori Kam
Thomas Monjalon
parent
9428310ae1
commit
e3dbbf718e
@ -23,6 +23,7 @@ int mlx5_regex_logtype;
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const struct rte_regexdev_ops mlx5_regexdev_ops = {
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.dev_info_get = mlx5_regex_info_get,
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.dev_configure = mlx5_regex_configure,
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};
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static struct ibv_device *
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@ -143,6 +144,7 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
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priv->regexdev->dev_ops = &mlx5_regexdev_ops;
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priv->regexdev->device = (struct rte_device *)pci_dev;
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priv->regexdev->data->dev_private = priv;
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priv->regexdev->state = RTE_REGEXDEV_READY;
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return 0;
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error:
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@ -7,16 +7,31 @@
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#include <rte_regexdev.h>
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struct mlx5_regex_sq {
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uint32_t nb_desc; /* Number of desc for this object. */
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};
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struct mlx5_regex_qp {
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uint32_t flags; /* QP user flags. */
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uint32_t nb_desc; /* Total number of desc for this qp. */
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struct mlx5_regex_sq *sqs; /* Pointer to sq array. */
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};
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struct mlx5_regex_priv {
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TAILQ_ENTRY(mlx5_regex_priv) next;
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struct ibv_context *ctx; /* Device context. */
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struct rte_pci_device *pci_dev;
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struct rte_regexdev *regexdev; /* Pointer to the RegEx dev. */
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uint16_t nb_queues; /* Number of queues. */
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struct mlx5_regex_qp *qps; /* Pointer to the qp array. */
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uint16_t nb_max_matches; /* Max number of matches. */
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};
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/* mlx5_rxp.c */
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int mlx5_regex_info_get(struct rte_regexdev *dev,
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struct rte_regexdev_info *info);
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int mlx5_regex_configure(struct rte_regexdev *dev,
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const struct rte_regexdev_config *cfg);
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/* mlx5_regex_devx.c */
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int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
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@ -4,11 +4,18 @@
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#include <rte_log.h>
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#include <rte_errno.h>
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#include <rte_malloc.h>
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#include <rte_regexdev.h>
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#include <rte_regexdev_core.h>
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#include <rte_regexdev_driver.h>
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#include <mlx5_glue.h>
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#include <mlx5_devx_cmds.h>
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#include <mlx5_prm.h>
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#include "mlx5_regex.h"
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#include "mlx5_regex_utils.h"
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#include "mlx5_rxp_csrs.h"
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#define MLX5_REGEX_MAX_MATCHES 255
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#define MLX5_REGEX_MAX_PAYLOAD_SIZE UINT16_MAX
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@ -27,3 +34,227 @@ mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,
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info->rule_flags = 0;
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return 0;
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}
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static int
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rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
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uint32_t address, uint32_t expected_value,
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uint32_t expected_mask, uint32_t timeout_ms, uint8_t id)
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{
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unsigned int i;
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int ret;
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ret = -EBUSY;
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for (i = 0; i < timeout_ms; i++) {
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if (mlx5_devx_regex_register_read(ctx, id, address, value))
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return -1;
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if ((*value & expected_mask) == expected_value) {
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ret = 0;
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break;
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}
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rte_delay_us(1000);
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}
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return ret;
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}
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static int
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rxp_start_engine(struct ibv_context *ctx, uint8_t id)
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{
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uint32_t ctrl;
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int ret;
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ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
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if (ret)
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return ret;
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ctrl |= MLX5_RXP_CSR_CTRL_GO;
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ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
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return ret;
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}
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static int
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rxp_stop_engine(struct ibv_context *ctx, uint8_t id)
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{
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uint32_t ctrl;
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int ret;
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ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
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if (ret)
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return ret;
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ctrl &= ~MLX5_RXP_CSR_CTRL_GO;
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ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
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return ret;
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}
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static int
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rxp_init_rtru(struct ibv_context *ctx, uint8_t id, uint32_t init_bits)
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{
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uint32_t ctrl_value;
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uint32_t poll_value;
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uint32_t expected_value;
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uint32_t expected_mask;
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int ret = 0;
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/* Read the rtru ctrl CSR. */
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ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
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&ctrl_value);
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if (ret)
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return -1;
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/* Clear any previous init modes. */
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ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK);
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if (ctrl_value & MLX5_RXP_RTRU_CSR_CTRL_INIT) {
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ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
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mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
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ctrl_value);
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}
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/* Set the init_mode bits in the rtru ctrl CSR. */
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ctrl_value |= init_bits;
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mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
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ctrl_value);
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/* Need to sleep for a short period after pulsing the rtru init bit. */
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rte_delay_us(20000);
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/* Poll the rtru status CSR until all the init done bits are set. */
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DRV_LOG(DEBUG, "waiting for RXP rule memory to complete init");
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/* Set the init bit in the rtru ctrl CSR. */
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ctrl_value |= MLX5_RXP_RTRU_CSR_CTRL_INIT;
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mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
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ctrl_value);
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/* Clear the init bit in the rtru ctrl CSR */
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ctrl_value &= ~MLX5_RXP_RTRU_CSR_CTRL_INIT;
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mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
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ctrl_value);
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/* Check that the following bits are set in the RTRU_CSR. */
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if (init_bits == MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2) {
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/* Must be incremental mode */
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expected_value = MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE |
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MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;
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} else {
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expected_value = MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE |
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MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE |
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MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;
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}
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expected_mask = expected_value;
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ret = rxp_poll_csr_for_value(ctx, &poll_value,
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MLX5_RXP_RTRU_CSR_STATUS,
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expected_value, expected_mask,
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MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
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if (ret)
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return ret;
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DRV_LOG(DEBUG, "rule memory initialise: 0x%08X", poll_value);
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/* Clear the init bit in the rtru ctrl CSR */
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ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
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mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
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ctrl_value);
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return 0;
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}
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static int
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rxp_init(struct mlx5_regex_priv *priv, uint8_t id)
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{
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uint32_t ctrl;
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uint32_t reg;
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struct ibv_context *ctx = priv->ctx;
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int ret;
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ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
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if (ret)
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return ret;
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if (ctrl & MLX5_RXP_CSR_CTRL_INIT) {
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ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
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ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
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ctrl);
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if (ret)
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return ret;
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}
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ctrl |= MLX5_RXP_CSR_CTRL_INIT;
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ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
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if (ret)
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return ret;
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ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
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ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
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rte_delay_us(20000);
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ret = rxp_poll_csr_for_value(ctx, &ctrl, MLX5_RXP_CSR_STATUS,
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MLX5_RXP_CSR_STATUS_INIT_DONE,
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MLX5_RXP_CSR_STATUS_INIT_DONE,
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MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
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if (ret)
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return ret;
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ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
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if (ret)
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return ret;
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ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
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ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
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ctrl);
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if (ret)
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return ret;
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rxp_init_rtru(ctx, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2);
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ret = rxp_init_rtru(ctx, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2);
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if (ret)
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return ret;
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ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CAPABILITY_5,
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®);
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if (ret)
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return ret;
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DRV_LOG(DEBUG, "max matches: %d, DDOS threshold: %d", reg >> 16,
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reg & 0xffff);
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ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_MAX_MATCH,
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priv->nb_max_matches);
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ret |= mlx5_devx_regex_register_write(ctx, id,
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MLX5_RXP_CSR_MAX_LATENCY, 0);
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ret |= mlx5_devx_regex_register_write(ctx, id,
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MLX5_RXP_CSR_MAX_PRI_THREAD, 0);
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return ret;
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}
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int
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mlx5_regex_configure(struct rte_regexdev *dev,
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const struct rte_regexdev_config *cfg)
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{
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struct mlx5_regex_priv *priv = dev->data->dev_private;
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int ret;
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uint8_t id;
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priv->nb_queues = cfg->nb_queue_pairs;
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priv->qps = rte_zmalloc(NULL, sizeof(struct mlx5_regex_qp) *
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priv->nb_queues, 0);
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if (!priv->nb_queues) {
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DRV_LOG(ERR, "can't allocate qps memory");
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rte_errno = ENOMEM;
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return -rte_errno;
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}
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priv->nb_max_matches = cfg->nb_max_matches;
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for (id = 0; id < 2; id++) {
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ret = rxp_stop_engine(priv->ctx, id);
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if (ret) {
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DRV_LOG(ERR, "can't stop engine.");
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rte_errno = ENODEV;
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return -rte_errno;
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}
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ret = rxp_init(priv, id);
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if (ret) {
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DRV_LOG(ERR, "can't init engine.");
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rte_errno = ENODEV;
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return -rte_errno;
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}
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ret = mlx5_devx_regex_register_write(priv->ctx, id,
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MLX5_RXP_CSR_MAX_MATCH,
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priv->nb_max_matches);
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if (ret) {
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DRV_LOG(ERR, "can't update number of matches.");
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rte_errno = ENODEV;
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goto configure_error;
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}
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ret = rxp_start_engine(priv->ctx, id);
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if (ret) {
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DRV_LOG(ERR, "can't start engine.");
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rte_errno = ENODEV;
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goto configure_error;
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}
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}
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return 0;
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configure_error:
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if (priv->qps)
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rte_free(priv->qps);
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return -rte_errno;
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}
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