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crypto/qat: support GMAC in GEN4 legacy mode

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Add AES-GMAC algorithm in legacy mode to generation 4 devices.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
This commit is contained in:
Arek Kusztal 2021-06-28 17:34:28 +01:00 committed by Akhil Goyal
parent c2c1ccaec2
commit e4beb311d2
3 changed files with 36 additions and 2 deletions
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27
drivers/crypto/qat/qat_sym_capabilities.h
View File

@ -1174,7 +1174,32 @@
}, \ }, \
}, } \ }, } \
}, } \ }, } \
} }, \
{ /* AES GMAC (AUTH) */ \
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
{.sym = { \
.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, \
{.auth = { \
.algo = RTE_CRYPTO_AUTH_AES_GMAC, \
.block_size = 16, \
.key_size = { \
.min = 16, \
.max = 32, \
.increment = 8 \
}, \
.digest_size = { \
.min = 8, \
.max = 16, \
.increment = 4 \
}, \
.iv_size = { \
.min = 0, \
.max = 12, \
.increment = 12 \
} \
}, } \
}, } \
} \

9
drivers/crypto/qat/qat_sym_session.c
View File

@ -710,6 +710,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
struct qat_sym_dev_private *internals = dev->data->dev_private; struct qat_sym_dev_private *internals = dev->data->dev_private;
const uint8_t *key_data = auth_xform->key.data; const uint8_t *key_data = auth_xform->key.data;
uint8_t key_length = auth_xform->key.length; uint8_t key_length = auth_xform->key.length;
enum qat_device_gen qat_dev_gen =
internals->qat_dev->qat_dev_gen;
session->aes_cmac = 0; session->aes_cmac = 0;
session->auth_key_length = auth_xform->key.length; session->auth_key_length = auth_xform->key.length;
@ -717,6 +719,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
session->auth_iv.length = auth_xform->iv.length; session->auth_iv.length = auth_xform->iv.length;
session->auth_mode = ICP_QAT_HW_AUTH_MODE1; session->auth_mode = ICP_QAT_HW_AUTH_MODE1;
session->is_auth = 1; session->is_auth = 1;
session->digest_length = auth_xform->digest_length;
switch (auth_xform->algo) { switch (auth_xform->algo) {
case RTE_CRYPTO_AUTH_SHA1: case RTE_CRYPTO_AUTH_SHA1:
@ -773,6 +776,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
session->auth_iv.length = AES_GCM_J0_LEN; session->auth_iv.length = AES_GCM_J0_LEN;
else else
session->is_iv12B = 1; session->is_iv12B = 1;
if (qat_dev_gen == QAT_GEN4) {
session->is_cnt_zero = 1;
session->is_ucs = 1;
}
break; break;
case RTE_CRYPTO_AUTH_SNOW3G_UIA2: case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
@ -858,7 +865,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
return -EINVAL; return -EINVAL;
} }
session->digest_length = auth_xform->digest_length;
return 0; return 0;
} }
@ -1814,6 +1820,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL
|| cdesc->is_cnt_zero
) )
hash->auth_counter.counter = 0; hash->auth_counter.counter = 0;
else { else {

2
drivers/crypto/qat/qat_sym_session.h
View File

@ -103,6 +103,8 @@ struct qat_sym_session {
uint8_t is_iv12B; uint8_t is_iv12B;
uint8_t is_gmac; uint8_t is_gmac;
uint8_t is_auth; uint8_t is_auth;
uint8_t is_cnt_zero;
/* Some generations need different setup of counter */
uint32_t slice_types; uint32_t slice_types;
enum qat_sym_proto_flag qat_proto_flag; enum qat_sym_proto_flag qat_proto_flag;
}; };