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eal/arm64: override I/O device read/write access

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Override the generic I/O device memory read/write access and implement it
using armv8 instructions for arm64.

Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
This commit is contained in:
Jerin Jacob 2017-01-18 06:51:26 +05:30 committed by Thomas Monjalon
parent a2c4cd8648
commit e783b81d44
2 changed files with 203 additions and 0 deletions
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4
lib/librte_eal/common/include/arch/arm/rte_io.h
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@ -38,7 +38,11 @@
extern "C" {
#endif
#ifdef RTE_ARCH_64
#include "rte_io_64.h"
#else
#include "generic/rte_io.h"
#endif
#ifdef __cplusplus
}

199
lib/librte_eal/common/include/arch/arm/rte_io_64.h Normal file
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@ -0,0 +1,199 @@
/*
* BSD LICENSE
*
* Copyright (C) Cavium networks Ltd. 2016.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Cavium networks nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _RTE_IO_ARM64_H_
#define _RTE_IO_ARM64_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define RTE_OVERRIDE_IO_H
#include "generic/rte_io.h"
#include "rte_atomic_64.h"
static inline uint8_t __attribute__((always_inline))
rte_read8_relaxed(const volatile void *addr)
{
uint8_t val;
asm volatile(
"ldrb %w[val], [%x[addr]]"
: [val] "=r" (val)
: [addr] "r" (addr));
return val;
}
static inline uint16_t __attribute__((always_inline))
rte_read16_relaxed(const volatile void *addr)
{
uint16_t val;
asm volatile(
"ldrh %w[val], [%x[addr]]"
: [val] "=r" (val)
: [addr] "r" (addr));
return val;
}
static inline uint32_t __attribute__((always_inline))
rte_read32_relaxed(const volatile void *addr)
{
uint32_t val;
asm volatile(
"ldr %w[val], [%x[addr]]"
: [val] "=r" (val)
: [addr] "r" (addr));
return val;
}
static inline uint64_t __attribute__((always_inline))
rte_read64_relaxed(const volatile void *addr)
{
uint64_t val;
asm volatile(
"ldr %x[val], [%x[addr]]"
: [val] "=r" (val)
: [addr] "r" (addr));
return val;
}
static inline void __attribute__((always_inline))
rte_write8_relaxed(uint8_t val, volatile void *addr)
{
asm volatile(
"strb %w[val], [%x[addr]]"
:
: [val] "r" (val), [addr] "r" (addr));
}
static inline void __attribute__((always_inline))
rte_write16_relaxed(uint16_t val, volatile void *addr)
{
asm volatile(
"strh %w[val], [%x[addr]]"
:
: [val] "r" (val), [addr] "r" (addr));
}
static inline void __attribute__((always_inline))
rte_write32_relaxed(uint32_t val, volatile void *addr)
{
asm volatile(
"str %w[val], [%x[addr]]"
:
: [val] "r" (val), [addr] "r" (addr));
}
static inline void __attribute__((always_inline))
rte_write64_relaxed(uint64_t val, volatile void *addr)
{
asm volatile(
"str %x[val], [%x[addr]]"
:
: [val] "r" (val), [addr] "r" (addr));
}
static inline uint8_t __attribute__((always_inline))
rte_read8(const volatile void *addr)
{
uint8_t val;
val = rte_read8_relaxed(addr);
rte_io_rmb();
return val;
}
static inline uint16_t __attribute__((always_inline))
rte_read16(const volatile void *addr)
{
uint16_t val;
val = rte_read16_relaxed(addr);
rte_io_rmb();
return val;
}
static inline uint32_t __attribute__((always_inline))
rte_read32(const volatile void *addr)
{
uint32_t val;
val = rte_read32_relaxed(addr);
rte_io_rmb();
return val;
}
static inline uint64_t __attribute__((always_inline))
rte_read64(const volatile void *addr)
{
uint64_t val;
val = rte_read64_relaxed(addr);
rte_io_rmb();
return val;
}
static inline void __attribute__((always_inline))
rte_write8(uint8_t value, volatile void *addr)
{
rte_io_wmb();
rte_write8_relaxed(value, addr);
}
static inline void __attribute__((always_inline))
rte_write16(uint16_t value, volatile void *addr)
{
rte_io_wmb();
rte_write16_relaxed(value, addr);
}
static inline void __attribute__((always_inline))
rte_write32(uint32_t value, volatile void *addr)
{
rte_io_wmb();
rte_write32_relaxed(value, addr);
}
static inline void __attribute__((always_inline))
rte_write64(uint64_t value, volatile void *addr)
{
rte_io_wmb();
rte_write64_relaxed(value, addr);
}
#ifdef __cplusplus
}
#endif
#endif /* _RTE_IO_ARM64_H_ */