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common/mlx5: split PCI relaxed ordering for read and write

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The current DevX implementation of the relaxed ordering feature is
enabling relaxed ordering usage only if both relaxed ordering read AND
write are supported.  In that case both relaxed ordering read and write
are activated.

This commit will optimize the usage of relaxed ordering by enabling it
when the read OR write features are supported.  Each relaxed ordering
type will be activated according to its own capability bit.

This will align the DevX flow with the verbs implementation of
ibv_reg_mr when using the flag IBV_ACCESS_RELAXED_ORDERING

Fixes: 53ac93f71a ("net/mlx5: create relaxed ordering memory regions")
Cc: stable@dpdk.org

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit is contained in:
Tal Shnaiderman 2020-11-03 10:51:22 +02:00 committed by Thomas Monjalon
parent 1e4593db1d
commit e82ddd28e3
8 changed files with 25 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/common/mlx5/mlx5_devx_cmds.c
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@ -267,10 +267,10 @@ mlx5_devx_cmd_mkey_create(void *ctx,
MLX5_SET(mkc, mkc, pd, attr->pd);
MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
if (attr->relaxed_ordering == 1) {
MLX5_SET(mkc, mkc, relaxed_ordering_write, 0x1);
MLX5_SET(mkc, mkc, relaxed_ordering_read, 0x1);
}
MLX5_SET(mkc, mkc, relaxed_ordering_write,
attr->relaxed_ordering_write);
MLX5_SET(mkc, mkc, relaxed_ordering_read,
attr->relaxed_ordering_read);
MLX5_SET64(mkc, mkc, start_addr, attr->addr);
MLX5_SET64(mkc, mkc, len, attr->size);
mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,

3
drivers/common/mlx5/mlx5_devx_cmds.h
View File

@ -20,7 +20,8 @@ struct mlx5_devx_mkey_attr {
uint32_t pd;
uint32_t log_entity_size;
uint32_t pg_access:1;
uint32_t relaxed_ordering:1;
uint32_t relaxed_ordering_write:1;
uint32_t relaxed_ordering_read:1;
struct mlx5_klm *klm_array;
int klm_num;
};

13
drivers/net/mlx5/linux/mlx5_os.c
View File

@ -1141,10 +1141,15 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
}
#endif /* HAVE_MLX5DV_DR_ACTION_FLOW_HIT */
/* Check relax ordering support. */
if (config->hca_attr.relaxed_ordering_write &&
config->hca_attr.relaxed_ordering_read &&
!haswell_broadwell_cpu)
sh->cmng.relaxed_ordering = 1;
if (!haswell_broadwell_cpu) {
sh->cmng.relaxed_ordering_write =
config->hca_attr.relaxed_ordering_write;
sh->cmng.relaxed_ordering_read =
config->hca_attr.relaxed_ordering_read;
} else {
sh->cmng.relaxed_ordering_read = 0;
sh->cmng.relaxed_ordering_write = 0;
}
/* Check for LRO support. */
if (config->dest_tir && config->hca_attr.lro_cap &&
config->dv_flow_en) {

3
drivers/net/mlx5/mlx5.h
View File

@ -467,7 +467,8 @@ struct mlx5_flow_counter_mng {
uint8_t pending_queries;
uint16_t pool_index;
uint8_t query_thread_on;
bool relaxed_ordering;
bool relaxed_ordering_read;
bool relaxed_ordering_write;
bool counter_fallback; /* Use counter fallback management. */
LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;

3
drivers/net/mlx5/mlx5_flow.c
View File

@ -6658,7 +6658,8 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh)
mkey_attr.pg_access = 0;
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
mkey_attr.relaxed_ordering = sh->cmng.relaxed_ordering;
mkey_attr.relaxed_ordering_write = sh->cmng.relaxed_ordering_write;
mkey_attr.relaxed_ordering_read = sh->cmng.relaxed_ordering_read;
mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
if (!mem_mng->dm) {
mlx5_glue->devx_umem_dereg(mem_mng->umem);

3
drivers/net/mlx5/mlx5_flow_age.c
View File

@ -156,7 +156,8 @@ mlx5_aso_devx_reg_mr(void *ctx, size_t length, struct mlx5_aso_devx_mr *mr,
mkey_attr.pg_access = 1;
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
mkey_attr.relaxed_ordering = 0;
mkey_attr.relaxed_ordering_read = 0;
mkey_attr.relaxed_ordering_write = 0;
mr->mkey = mlx5_devx_cmd_mkey_create(ctx, &mkey_attr);
if (!mr->mkey) {
DRV_LOG(ERR, "Failed to create direct Mkey.");

3
drivers/vdpa/mlx5/mlx5_vdpa_lm.c
View File

@ -43,7 +43,8 @@ mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base,
.pg_access = 1,
.klm_array = NULL,
.klm_num = 0,
.relaxed_ordering = 0,
.relaxed_ordering_read = 0,
.relaxed_ordering_write = 0,
};
struct mlx5_devx_virtq_attr attr = {
.type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS,

3
drivers/vdpa/mlx5/mlx5_vdpa_mem.c
View File

@ -223,7 +223,8 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv)
mkey_attr.pg_access = 1;
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
mkey_attr.relaxed_ordering = 0;
mkey_attr.relaxed_ordering_read = 0;
mkey_attr.relaxed_ordering_write = 0;
entry->mkey = mlx5_devx_cmd_mkey_create(priv->ctx, &mkey_attr);
if (!entry->mkey) {
DRV_LOG(ERR, "Failed to create direct Mkey.");