d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

net/octeontx: fix build with SVE

Browse Source 
Building with gcc 10.2 with SVE extension enabled got error:

{standard input}: Assembler messages:
{standard input}:91: Error: selected processor does not support `addvl x4,x8,#-1'
{standard input}:95: Error: selected processor does not support `ptrue p1.d,all'
{standard input}:135: Error: selected processor does not support `whilelo p2.d,xzr,x5'
{standard input}:137: Error: selected processor does not support `decb x1'

This is because inline assembly code explicitly resets cpu model to
not have SVE support. Thus SVE instructions generated by compiler
auto vectorization got rejected by assembler.

Added SVE to the cpu model specified by inline assembly for SVE support.
Not replacing the inline assembly with C atomics because the driver relies
on specific LSE instruction to interface to co-processor [1].

Fixes: f0c7bb1bf7 ("net/octeontx/base: add octeontx IO operations")
Cc: stable@dpdk.org

[1] https://mails.dpdk.org/archives/dev/2021-January/196092.html

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
This commit is contained in:
Ruifeng Wang 2021-01-12 02:57:06 +00:00 committed by David Marchand
parent 21c4f1c7b2
commit e88bd47467
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/net/octeontx/base/octeontx_io.h
View File

@ -52,6 +52,11 @@ do { \
#endif
#if defined(RTE_ARCH_ARM64)
#if defined(__ARM_FEATURE_SVE)
#define __LSE_PREAMBLE " .cpu generic+lse+sve\n"
#else
#define __LSE_PREAMBLE " .cpu generic+lse\n"
#endif
/**
* Perform an atomic fetch-and-add operation.
*/
@ -61,7 +66,7 @@ octeontx_reg_ldadd_u64(void *addr, int64_t off)
uint64_t old_val;
__asm__ volatile(
" .cpu generic+lse\n"
__LSE_PREAMBLE
" ldadd %1, %0, [%2]\n"
: "=r" (old_val) : "r" (off), "r" (addr) : "memory");
@ -98,12 +103,13 @@ octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[],
/* LDEOR initiates atomic transfer to I/O device */
__asm__ volatile(
" .cpu generic+lse\n"
__LSE_PREAMBLE
" ldeor xzr, %0, [%1]\n"
: "=r" (result) : "r" (ioreg_va) : "memory");
} while (!result);
}
#undef __LSE_PREAMBLE
#else
static inline uint64_t