d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

config: rename option for C11 memory model

Browse Source 
Keep only single config option RTE_USE_C11_MEM_MODEL for C11 memory
model, so all modules can leverage C11 atomic extension by enable this
option.

Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
This commit is contained in:
Phil Yang 2018-10-08 17:11:43 +08:00 committed by Thomas Monjalon
parent b78f32cff9
commit ede56cc18d
5 changed files with 11 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
config/arm/meson.build
View File

@ -53,7 +53,7 @@ flags_cavium = [
['RTE_MAX_NUMA_NODES', 2],
['RTE_MAX_LCORE', 96],
['RTE_MAX_VFIO_GROUPS', 128],
['RTE_RING_USE_C11_MEM_MODEL', false]]
['RTE_USE_C11_MEM_MODEL', false]]
flags_dpaa = [
['RTE_MACHINE', '"dpaa"'],
['RTE_CACHE_LINE_SIZE', 64],

4
config/common_armv8a_linuxapp
View File

@ -17,6 +17,8 @@ CONFIG_RTE_FORCE_INTRINSICS=y
# to address minimum DMA alignment across all arm64 implementations.
CONFIG_RTE_CACHE_LINE_SIZE=128
CONFIG_RTE_USE_C11_MEM_MODEL=y
# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
# to determine the best threshold in code. Refer to notes in source file
# (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info.
@ -29,8 +31,6 @@ CONFIG_RTE_ARCH_ARM64_MEMCPY=n
#CONFIG_RTE_ARM64_MEMCPY_ALIGN_MASK=0xF
#CONFIG_RTE_ARM64_MEMCPY_STRICT_ALIGN=n
CONFIG_RTE_RING_USE_C11_MEM_MODEL=y
CONFIG_RTE_LIBRTE_FM10K_PMD=n
CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n
CONFIG_RTE_LIBRTE_AVP_PMD=n

6
config/common_base
View File

@ -55,6 +55,11 @@ CONFIG_RTE_MAJOR_ABI=
#
CONFIG_RTE_CACHE_LINE_SIZE=64
#
# Memory model
#
CONFIG_RTE_USE_C11_MEM_MODEL=n
#
# Compile Environment Abstraction Layer
#
@ -698,7 +703,6 @@ CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y
# Compile librte_ring
#
CONFIG_RTE_LIBRTE_RING=y
CONFIG_RTE_RING_USE_C11_MEM_MODEL=n
#
# Compile librte_mempool

2
config/defconfig_arm64-thunderx-linuxapp-gcc
View File

@ -7,10 +7,10 @@
CONFIG_RTE_MACHINE="thunderx"
CONFIG_RTE_CACHE_LINE_SIZE=128
CONFIG_RTE_USE_C11_MEM_MODEL=n
CONFIG_RTE_MAX_NUMA_NODES=2
CONFIG_RTE_MAX_LCORE=96
CONFIG_RTE_MAX_VFIO_GROUPS=128
CONFIG_RTE_RING_USE_C11_MEM_MODEL=n
#
# Compile PMD for octeontx sso event device

4
lib/librte_ring/rte_ring.h
View File

@ -303,11 +303,11 @@ void rte_ring_dump(FILE *f, const struct rte_ring *r);
* There are 2 choices for the users
* 1.use rmb() memory barrier
* 2.use one-direcion load_acquire/store_release barrier,defined by
* CONFIG_RTE_RING_USE_C11_MEM_MODEL=y
* CONFIG_RTE_USE_C11_MEM_MODEL=y
* It depends on performance test results.
* By default, move common functions to rte_ring_generic.h
*/
#ifdef RTE_RING_USE_C11_MEM_MODEL
#ifdef RTE_USE_C11_MEM_MODEL
#include "rte_ring_c11_mem.h"
#else
#include "rte_ring_generic.h"