mempool/octeontx2: add optimized dequeue operation for arm64
This patch adds an optimized arm64 instruction based routine to leverage CPU pipeline characteristics of octeontx2. The theme is to fill the pipeline with CASP operations as much HW can do so that HW can do alloc() HW ops in full throttle. Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
This commit is contained in:
Pavan Nikhilesh
Thomas Monjalon
parent
d7a0da3c00
commit
ee338015e7
@ -37,6 +37,303 @@ npa_lf_aura_op_alloc_one(const int64_t wdata, int64_t * const addr,
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return -ENOENT;
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}
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#if defined(RTE_ARCH_ARM64)
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static __rte_noinline int
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npa_lf_aura_op_search_alloc(const int64_t wdata, int64_t * const addr,
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void **obj_table, unsigned int n)
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{
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uint8_t i;
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for (i = 0; i < n; i++) {
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if (obj_table[i] != NULL)
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continue;
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if (npa_lf_aura_op_alloc_one(wdata, addr, obj_table, i))
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return -ENOENT;
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}
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return 0;
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}
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/*
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* Some versions of the compiler don't have support for __int128_t for
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* CASP inline-asm. i.e. if the optimization level is reduced to -O0 the
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* CASP restrictions aren't followed and the compiler might end up violation the
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* CASP rules. Fix it by explicitly providing ((optimize("-O3"))).
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*
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* Example:
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* ccSPMGzq.s:1648: Error: reg pair must start from even reg at
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* operand 1 - `casp x21,x22,x0,x1,[x19]'
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*/
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static __attribute__((optimize("-O3"))) __rte_noinline int __hot
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npa_lf_aura_op_alloc_bulk(const int64_t wdata, int64_t * const addr,
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unsigned int n, void **obj_table)
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{
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const __uint128_t wdata128 = ((__uint128_t)wdata << 64) | wdata;
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uint64x2_t failed = vdupq_n_u64(~0);
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switch (n) {
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case 32:
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{
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__uint128_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
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__uint128_t t10, t11;
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asm volatile (
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".cpu generic+lse\n"
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"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t4], %H[t4], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t5], %H[t5], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t6], %H[t6], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t7], %H[t7], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t8], %H[t8], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t9], %H[t9], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t10], %H[t10], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t11], %H[t11], %[wdata], %H[wdata], [%[loc]]\n"
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"fmov d16, %[t0]\n"
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"fmov v16.D[1], %H[t0]\n"
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"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n"
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"fmov d17, %[t1]\n"
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"fmov v17.D[1], %H[t1]\n"
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"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\n"
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"fmov d18, %[t2]\n"
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"fmov v18.D[1], %H[t2]\n"
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"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\n"
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"fmov d19, %[t3]\n"
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"fmov v19.D[1], %H[t3]\n"
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"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\n"
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"and %[failed].16B, %[failed].16B, v16.16B\n"
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"and %[failed].16B, %[failed].16B, v17.16B\n"
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"and %[failed].16B, %[failed].16B, v18.16B\n"
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"and %[failed].16B, %[failed].16B, v19.16B\n"
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"fmov d20, %[t4]\n"
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"fmov v20.D[1], %H[t4]\n"
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"fmov d21, %[t5]\n"
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"fmov v21.D[1], %H[t5]\n"
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"fmov d22, %[t6]\n"
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"fmov v22.D[1], %H[t6]\n"
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"fmov d23, %[t7]\n"
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"fmov v23.D[1], %H[t7]\n"
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"and %[failed].16B, %[failed].16B, v20.16B\n"
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"and %[failed].16B, %[failed].16B, v21.16B\n"
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"and %[failed].16B, %[failed].16B, v22.16B\n"
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"and %[failed].16B, %[failed].16B, v23.16B\n"
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"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\n"
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"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\n"
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"fmov d16, %[t8]\n"
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"fmov v16.D[1], %H[t8]\n"
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"fmov d17, %[t9]\n"
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"fmov v17.D[1], %H[t9]\n"
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"fmov d18, %[t10]\n"
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"fmov v18.D[1], %H[t10]\n"
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"fmov d19, %[t11]\n"
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"fmov v19.D[1], %H[t11]\n"
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"and %[failed].16B, %[failed].16B, v16.16B\n"
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"and %[failed].16B, %[failed].16B, v17.16B\n"
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"and %[failed].16B, %[failed].16B, v18.16B\n"
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"and %[failed].16B, %[failed].16B, v19.16B\n"
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"fmov d20, %[t0]\n"
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"fmov v20.D[1], %H[t0]\n"
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"fmov d21, %[t1]\n"
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"fmov v21.D[1], %H[t1]\n"
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"fmov d22, %[t2]\n"
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"fmov v22.D[1], %H[t2]\n"
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"fmov d23, %[t3]\n"
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"fmov v23.D[1], %H[t3]\n"
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"and %[failed].16B, %[failed].16B, v20.16B\n"
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"and %[failed].16B, %[failed].16B, v21.16B\n"
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"and %[failed].16B, %[failed].16B, v22.16B\n"
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"and %[failed].16B, %[failed].16B, v23.16B\n"
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"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\n"
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"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\n"
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: "+Q" (*addr), [failed] "=&w" (failed),
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[t0] "=&r" (t0), [t1] "=&r" (t1), [t2] "=&r" (t2),
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[t3] "=&r" (t3), [t4] "=&r" (t4), [t5] "=&r" (t5),
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[t6] "=&r" (t6), [t7] "=&r" (t7), [t8] "=&r" (t8),
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[t9] "=&r" (t9), [t10] "=&r" (t10), [t11] "=&r" (t11)
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: [wdata] "r" (wdata128), [dst] "r" (obj_table),
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[loc] "r" (addr)
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: "memory", "v16", "v17", "v18",
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"v19", "v20", "v21", "v22", "v23"
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);
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break;
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}
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case 16:
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{
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__uint128_t t0, t1, t2, t3, t4, t5, t6, t7;
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asm volatile (
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".cpu generic+lse\n"
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"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t4], %H[t4], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t5], %H[t5], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t6], %H[t6], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t7], %H[t7], %[wdata], %H[wdata], [%[loc]]\n"
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"fmov d16, %[t0]\n"
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"fmov v16.D[1], %H[t0]\n"
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"fmov d17, %[t1]\n"
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"fmov v17.D[1], %H[t1]\n"
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"fmov d18, %[t2]\n"
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"fmov v18.D[1], %H[t2]\n"
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"fmov d19, %[t3]\n"
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"fmov v19.D[1], %H[t3]\n"
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"and %[failed].16B, %[failed].16B, v16.16B\n"
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"and %[failed].16B, %[failed].16B, v17.16B\n"
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"and %[failed].16B, %[failed].16B, v18.16B\n"
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"and %[failed].16B, %[failed].16B, v19.16B\n"
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"fmov d20, %[t4]\n"
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"fmov v20.D[1], %H[t4]\n"
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"fmov d21, %[t5]\n"
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"fmov v21.D[1], %H[t5]\n"
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"fmov d22, %[t6]\n"
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"fmov v22.D[1], %H[t6]\n"
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"fmov d23, %[t7]\n"
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"fmov v23.D[1], %H[t7]\n"
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"and %[failed].16B, %[failed].16B, v20.16B\n"
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"and %[failed].16B, %[failed].16B, v21.16B\n"
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"and %[failed].16B, %[failed].16B, v22.16B\n"
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"and %[failed].16B, %[failed].16B, v23.16B\n"
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"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\n"
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"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\n"
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: "+Q" (*addr), [failed] "=&w" (failed),
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[t0] "=&r" (t0), [t1] "=&r" (t1), [t2] "=&r" (t2),
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[t3] "=&r" (t3), [t4] "=&r" (t4), [t5] "=&r" (t5),
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[t6] "=&r" (t6), [t7] "=&r" (t7)
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: [wdata] "r" (wdata128), [dst] "r" (obj_table),
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[loc] "r" (addr)
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: "memory", "v16", "v17", "v18", "v19",
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"v20", "v21", "v22", "v23"
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);
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break;
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}
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case 8:
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{
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__uint128_t t0, t1, t2, t3;
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asm volatile (
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".cpu generic+lse\n"
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"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\n"
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"fmov d16, %[t0]\n"
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"fmov v16.D[1], %H[t0]\n"
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"fmov d17, %[t1]\n"
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"fmov v17.D[1], %H[t1]\n"
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"fmov d18, %[t2]\n"
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"fmov v18.D[1], %H[t2]\n"
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"fmov d19, %[t3]\n"
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"fmov v19.D[1], %H[t3]\n"
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"and %[failed].16B, %[failed].16B, v16.16B\n"
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"and %[failed].16B, %[failed].16B, v17.16B\n"
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"and %[failed].16B, %[failed].16B, v18.16B\n"
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"and %[failed].16B, %[failed].16B, v19.16B\n"
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"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\n"
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: "+Q" (*addr), [failed] "=&w" (failed),
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[t0] "=&r" (t0), [t1] "=&r" (t1), [t2] "=&r" (t2),
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[t3] "=&r" (t3)
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: [wdata] "r" (wdata128), [dst] "r" (obj_table),
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[loc] "r" (addr)
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: "memory", "v16", "v17", "v18", "v19"
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);
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break;
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}
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case 4:
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{
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__uint128_t t0, t1;
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asm volatile (
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".cpu generic+lse\n"
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"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n"
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"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\n"
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"fmov d16, %[t0]\n"
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"fmov v16.D[1], %H[t0]\n"
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"fmov d17, %[t1]\n"
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"fmov v17.D[1], %H[t1]\n"
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"and %[failed].16B, %[failed].16B, v16.16B\n"
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"and %[failed].16B, %[failed].16B, v17.16B\n"
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"st1 { v16.2d, v17.2d}, [%[dst]], 32\n"
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: "+Q" (*addr), [failed] "=&w" (failed),
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[t0] "=&r" (t0), [t1] "=&r" (t1)
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: [wdata] "r" (wdata128), [dst] "r" (obj_table),
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[loc] "r" (addr)
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: "memory", "v16", "v17"
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);
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break;
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}
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case 2:
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{
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__uint128_t t0;
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asm volatile (
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".cpu generic+lse\n"
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"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n"
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"fmov d16, %[t0]\n"
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"fmov v16.D[1], %H[t0]\n"
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"and %[failed].16B, %[failed].16B, v16.16B\n"
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"st1 { v16.2d}, [%[dst]], 16\n"
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: "+Q" (*addr), [failed] "=&w" (failed),
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[t0] "=&r" (t0)
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: [wdata] "r" (wdata128), [dst] "r" (obj_table),
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[loc] "r" (addr)
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: "memory", "v16"
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);
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break;
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}
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case 1:
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return npa_lf_aura_op_alloc_one(wdata, addr, obj_table, 0);
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}
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if (unlikely(!(vgetq_lane_u64(failed, 0) & vgetq_lane_u64(failed, 1))))
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return npa_lf_aura_op_search_alloc(wdata, addr, (void **)
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((char *)obj_table - (sizeof(uint64_t) * n)), n);
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return 0;
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}
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static __rte_noinline void
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otx2_npa_clear_alloc(struct rte_mempool *mp, void **obj_table, unsigned int n)
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{
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unsigned int i;
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for (i = 0; i < n; i++) {
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if (obj_table[i] != NULL) {
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otx2_npa_enq(mp, &obj_table[i], 1);
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obj_table[i] = NULL;
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}
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}
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}
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static inline int __hot
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otx2_npa_deq_arm64(struct rte_mempool *mp, void **obj_table, unsigned int n)
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{
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const int64_t wdata = npa_lf_aura_handle_to_aura(mp->pool_id);
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void **obj_table_bak = obj_table;
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const unsigned int nfree = n;
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unsigned int parts;
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int64_t * const addr = (int64_t * const)
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(npa_lf_aura_handle_to_base(mp->pool_id) +
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NPA_LF_AURA_OP_ALLOCX(0));
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while (n) {
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parts = n > 31 ? 32 : rte_align32prevpow2(n);
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n -= parts;
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if (unlikely(npa_lf_aura_op_alloc_bulk(wdata, addr,
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parts, obj_table))) {
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otx2_npa_clear_alloc(mp, obj_table_bak, nfree - n);
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return -ENOENT;
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}
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obj_table += parts;
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}
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return 0;
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}
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#endif
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static inline int __hot
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otx2_npa_deq(struct rte_mempool *mp, void **obj_table, unsigned int n)
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{
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@ -463,7 +760,11 @@ static struct rte_mempool_ops otx2_npa_ops = {
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.get_count = otx2_npa_get_count,
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.calc_mem_size = otx2_npa_calc_mem_size,
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.populate = otx2_npa_populate,
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#if defined(RTE_ARCH_ARM64)
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.dequeue = otx2_npa_deq_arm64,
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#else
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.dequeue = otx2_npa_deq,
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#endif
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};
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MEMPOOL_REGISTER_OPS(otx2_npa_ops);
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