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i40e: initialize flow director flexible payload setting

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set flexible payload related registers to default value at initialization time.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
This commit is contained in:
Jingjing Wu 2014-11-21 08:46:37 +08:00 committed by Thomas Monjalon
parent 71d35259ff
commit f05ec7d77e
3 changed files with 114 additions and 0 deletions
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36
lib/librte_pmd_i40e/i40e_ethdev.c
View File

@ -316,6 +316,35 @@ static struct rte_driver rte_i40e_driver = {
PMD_REGISTER_DRIVER(rte_i40e_driver);
/*
* Initialize registers for flexible payload, which should be set by NVM.
* This should be removed from code once it is fixed in NVM.
*/
#ifndef I40E_GLQF_ORT
#define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
#endif
#ifndef I40E_GLQF_PIT
#define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
#endif
static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
{
I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
/* GLQF_PIT Registers */
I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
}
static int
eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
struct rte_eth_dev *dev)
@ -379,6 +408,13 @@ eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
return ret;
}
/*
* To work around the NVM issue,initialize registers
* for flexible payload by software.
* It should be removed once issues are fixed in NVM.
*/
i40e_flex_payload_reg_init(hw);
/* Initialize the parameters for adminq */
i40e_init_adminq_parameter(hw);
ret = i40e_init_adminq(hw);

35
lib/librte_pmd_i40e/i40e_ethdev.h
View File

@ -80,6 +80,17 @@
#define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
#define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
/* index flex payload per layer */
enum i40e_flxpld_layer_idx {
I40E_FLXPLD_L2_IDX = 0,
I40E_FLXPLD_L3_IDX = 1,
I40E_FLXPLD_L4_IDX = 2,
I40E_MAX_FLXPLD_LAYER = 3,
};
#define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
#define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
#define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
/* i40e flags */
#define I40E_FLAG_RSS (1ULL << 0)
#define I40E_FLAG_DCB (1ULL << 1)
@ -266,6 +277,24 @@ struct i40e_vmdq_info {
struct i40e_vsi *vsi;
};
/*
* Structure to store flex pit for flow diretor.
*/
struct i40e_fdir_flex_pit {
uint8_t src_offset; /* offset in words from the beginning of payload */
uint8_t size; /* size in words */
uint8_t dst_offset; /* offset in words of flexible payload */
};
struct i40e_fdir_flex_mask {
uint8_t word_mask; /**< Bit i enables word i of flexible payload */
struct {
uint8_t offset;
uint16_t mask;
} bitmask[I40E_FDIR_BITMASK_NUM_WORD];
};
#define I40E_FILTER_PCTYPE_MAX 64
/*
* A structure used to define fields of a FDIR related info.
*/
@ -276,6 +305,12 @@ struct i40e_fdir_info {
struct i40e_rx_queue *rxq;
void *prg_pkt; /* memory for fdir program packet */
uint64_t dma_addr; /* physic address of packet memory*/
/*
* the rule how bytes stream is extracted as flexible payload
* for each payload layer, the setting can up to three elements
*/
struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
};
/*

43
lib/librte_pmd_i40e/i40e_fdir.c
View File

@ -264,6 +264,47 @@ i40e_fdir_empty(struct i40e_hw *hw)
return 0;
}
/*
* Initialize the configuration about bytes stream extracted as flexible payload
* and mask setting
*/
static inline void
i40e_init_flx_pld(struct i40e_pf *pf)
{
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
uint8_t pctype;
int i, index;
/*
* Define the bytes stream extracted as flexible payload in
* field vector. By default, select 8 words from the beginning
* of payload as flexible payload.
*/
for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
index = i * I40E_MAX_FLXPLD_FIED;
pf->fdir.flex_set[index].src_offset = 0;
pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
pf->fdir.flex_set[index].dst_offset = 0;
I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
I40E_WRITE_REG(hw,
I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
I40E_WRITE_REG(hw,
I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
}
/* initialize the masks */
for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {
pf->fdir.flex_mask[pctype].word_mask = 0;
I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
}
}
}
/*
* Configure flow director related setting
*/
@ -294,6 +335,8 @@ i40e_fdir_configure(struct rte_eth_dev *dev)
/* enable FDIR filter */
val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
i40e_init_flx_pld(pf); /* set flex config to default value */
} else {
/* disable FDIR filter */
val &= ~I40E_PFQF_CTL_0_FD_ENA_MASK;