net/octeontx/base: add octeontx IO operations
Adding octeontx specific io operations. Added a stub for building against non octeontx targets. Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
This commit is contained in:
Jerin Jacob
Ferruh Yigit
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3c0511741c
commit
f0c7bb1bf7
156
drivers/net/octeontx/base/octeontx_io.h
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156
drivers/net/octeontx/base/octeontx_io.h
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/*
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* BSD LICENSE
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*
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* Copyright (C) Cavium Inc. 2017. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Cavium networks nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __OCTEONTX_IO_H__
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#define __OCTEONTX_IO_H__
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#include <stddef.h>
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#include <stdint.h>
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#include <rte_io.h>
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/* In Cavium OcteonTX SoC, all accesses to the device registers are
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* implicitly strongly ordered. So, The relaxed version of IO operation is
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* safe to use with out any IO memory barriers.
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*/
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#define octeontx_read64 rte_read64_relaxed
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#define octeontx_write64 rte_write64_relaxed
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/* ARM64 specific functions */
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#if defined(RTE_ARCH_ARM64)
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#define octeontx_prefetch_store_keep(_ptr) ({\
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asm volatile("prfm pstl1keep, %a0\n" : : "p" (_ptr)); })
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#define octeontx_load_pair(val0, val1, addr) ({ \
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asm volatile( \
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"ldp %x[x0], %x[x1], [%x[p1]]" \
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:[x0]"=r"(val0), [x1]"=r"(val1) \
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:[p1]"r"(addr) \
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); })
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#define octeontx_store_pair(val0, val1, addr) ({ \
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asm volatile( \
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"stp %x[x0], %x[x1], [%x[p1]]" \
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::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
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); })
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#else /* Un optimized functions for building on non arm64 arch */
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#define octeontx_prefetch_store_keep(_ptr) do {} while (0)
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#define octeontx_load_pair(val0, val1, addr) \
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do { \
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val0 = rte_read64(addr); \
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val1 = rte_read64(((uint8_t *)addr) + 8); \
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} while (0)
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#define octeontx_store_pair(val0, val1, addr) \
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do { \
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rte_write64(val0, addr); \
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rte_write64(val1, (((uint8_t *)addr) + 8)); \
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} while (0)
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#endif
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#if defined(RTE_ARCH_ARM64)
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/**
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* Perform an atomic fetch-and-add operation.
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*/
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static inline uint64_t
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octeontx_reg_ldadd_u64(void *addr, int64_t off)
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{
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uint64_t old_val;
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__asm__ volatile(
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" .cpu generic+lse\n"
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" ldadd %1, %0, [%2]\n"
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: "=r" (old_val) : "r" (off), "r" (addr) : "memory");
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return old_val;
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}
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/**
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* Perform a LMTST operation - an atomic write of up to 128 byte to
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* an I/O block that supports this operation type.
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*
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* @param lmtline_va is the address where LMTLINE is mapped
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* @param ioreg_va is the virtual address of the device register
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* @param cmdbuf is the array of peripheral commands to execute
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* @param cmdsize is the number of 64-bit words in 'cmdbuf'
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*
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* @return N/A
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*/
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static inline void
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octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[],
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uint64_t cmdsize)
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{
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uint64_t result;
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uint64_t word_count;
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uint64_t *lmtline = lmtline_va;
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word_count = cmdsize;
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do {
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/* Copy commands to LMTLINE */
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for (result = 0; result < word_count; result += 2) {
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lmtline[result + 0] = cmdbuf[result + 0];
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lmtline[result + 1] = cmdbuf[result + 1];
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}
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/* LDEOR initiates atomic transfer to I/O device */
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__asm__ volatile(
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" .cpu generic+lse\n"
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" ldeor xzr, %0, [%1]\n"
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: "=r" (result) : "r" (ioreg_va) : "memory");
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} while (!result);
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}
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#else
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static inline uint64_t
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octeontx_reg_ldadd_u64(void *addr, int64_t off)
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{
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RTE_SET_USED(addr);
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RTE_SET_USED(off);
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return 0;
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}
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static inline void
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octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[],
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uint64_t cmdsize)
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{
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RTE_SET_USED(lmtline_va);
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RTE_SET_USED(ioreg_va);
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RTE_SET_USED(cmdbuf);
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RTE_SET_USED(cmdsize);
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}
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#endif
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#endif /* __OCTEONTX_IO_H__ */
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