mlx4: add L3/L4 checksum offload
Mellanox ConnectX-3 adapters can handle L3 (IPv4) and L4 (TCP, UDP, TCP6, UDP6) RX checksums validation and TX checksums generation, with and without 802.1Q (VLAN) headers. Signed-off-by: Gilad Berman <giladb@mellanox.com> Signed-off-by: Olga Shern <olgas@mellanox.com> Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
This commit is contained in:
Gilad Berman
Thomas Monjalon
parent
9755174d3a
commit
f0fda21d19
@ -139,6 +139,12 @@ static inline void wr_id_t_check(void)
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(void)wr_id_t_check;
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}
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/* Transpose flags. Useful to convert IBV to DPDK flags. */
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#define TRANSPOSE(val, from, to) \
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(((from) >= (to)) ? \
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(((val) & (from)) / ((from) / (to))) : \
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(((val) & (from)) * ((to) / (from))))
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struct mlx4_rxq_stats {
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unsigned int idx; /**< Mapping index. */
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#ifdef MLX4_PMD_SOFT_COUNTERS
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@ -196,6 +202,7 @@ struct rxq {
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struct rxq_elt (*no_sp)[]; /* RX elements. */
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} elts;
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unsigned int sp:1; /* Use scattered RX elements. */
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unsigned int csum:1; /* Enable checksum offloading. */
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uint32_t mb_len; /* Length of a mp-issued mbuf. */
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struct mlx4_rxq_stats stats; /* RX queue counters. */
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unsigned int socket; /* CPU socket ID for allocations. */
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@ -268,6 +275,7 @@ struct priv {
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unsigned int hw_qpg:1; /* QP groups are supported. */
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unsigned int hw_tss:1; /* TSS is supported. */
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unsigned int hw_rss:1; /* RSS is supported. */
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unsigned int hw_csum:1; /* Checksum offload is supported. */
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unsigned int rss:1; /* RSS is enabled. */
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unsigned int vf:1; /* This is a VF device. */
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#ifdef INLINE_RECV
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@ -1233,6 +1241,10 @@ mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
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++elts_comp;
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send_flags |= IBV_EXP_QP_BURST_SIGNALED;
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}
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/* Should we enable HW CKSUM offload */
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if (buf->ol_flags &
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(PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
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send_flags |= IBV_EXP_QP_BURST_IP_CSUM;
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if (likely(segs == 1)) {
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uintptr_t addr;
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uint32_t length;
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@ -2404,6 +2416,36 @@ rxq_cleanup(struct rxq *rxq)
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memset(rxq, 0, sizeof(*rxq));
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}
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/**
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* Translate RX completion flags to offload flags.
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*
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* @param[in] rxq
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* Pointer to RX queue structure.
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* @param flags
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* RX completion flags returned by poll_length_flags().
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*
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* @return
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* Offload flags (ol_flags) for struct rte_mbuf.
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*/
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static inline uint32_t
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rxq_cq_to_ol_flags(const struct rxq *rxq, uint32_t flags)
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{
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uint32_t ol_flags;
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ol_flags =
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TRANSPOSE(flags, IBV_EXP_CQ_RX_IPV4_PACKET, PKT_RX_IPV4_HDR) |
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TRANSPOSE(flags, IBV_EXP_CQ_RX_IPV6_PACKET, PKT_RX_IPV6_HDR);
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if (rxq->csum)
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ol_flags |=
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TRANSPOSE(~flags,
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IBV_EXP_CQ_RX_IP_CSUM_OK,
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PKT_RX_IP_CKSUM_BAD) |
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TRANSPOSE(~flags,
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IBV_EXP_CQ_RX_TCP_UDP_CSUM_OK,
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PKT_RX_L4_CKSUM_BAD);
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return ol_flags;
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}
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static uint16_t
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mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
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@ -2448,6 +2490,7 @@ mlx4_rx_burst_sp(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
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struct rte_mbuf **pkt_buf_next = &pkt_buf;
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unsigned int seg_headroom = RTE_PKTMBUF_HEADROOM;
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unsigned int j = 0;
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uint32_t flags;
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/* Sanity checks. */
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#ifdef NDEBUG
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@ -2458,7 +2501,8 @@ mlx4_rx_burst_sp(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
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assert(wr->num_sge == elemof(elt->sges));
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assert(elts_head < rxq->elts_n);
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assert(rxq->elts_head < rxq->elts_n);
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ret = rxq->if_cq->poll_length(rxq->cq, NULL, NULL);
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ret = rxq->if_cq->poll_length_flags(rxq->cq, NULL, NULL,
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&flags);
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if (unlikely(ret < 0)) {
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struct ibv_wc wc;
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int wcs_n;
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@ -2584,7 +2628,7 @@ mlx4_rx_burst_sp(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
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NB_SEGS(pkt_buf) = j;
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PORT(pkt_buf) = rxq->port_id;
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PKT_LEN(pkt_buf) = pkt_buf_len;
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pkt_buf->ol_flags = 0;
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pkt_buf->ol_flags = rxq_cq_to_ol_flags(rxq, flags);
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/* Return packet. */
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*(pkts++) = pkt_buf;
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@ -2661,6 +2705,7 @@ mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
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struct rte_mbuf *seg = (void *)((uintptr_t)elt->sge.addr -
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WR_ID(wr_id).offset);
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struct rte_mbuf *rep;
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uint32_t flags;
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/* Sanity checks. */
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assert(WR_ID(wr_id).id < rxq->elts_n);
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@ -2668,7 +2713,8 @@ mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
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assert(wr->num_sge == 1);
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assert(elts_head < rxq->elts_n);
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assert(rxq->elts_head < rxq->elts_n);
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ret = rxq->if_cq->poll_length(rxq->cq, NULL, NULL);
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ret = rxq->if_cq->poll_length_flags(rxq->cq, NULL, NULL,
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&flags);
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if (unlikely(ret < 0)) {
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struct ibv_wc wc;
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int wcs_n;
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@ -2742,7 +2788,7 @@ mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
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NEXT(seg) = NULL;
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PKT_LEN(seg) = len;
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DATA_LEN(seg) = len;
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seg->ol_flags = 0;
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seg->ol_flags = rxq_cq_to_ol_flags(rxq, flags);
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/* Return packet. */
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*(pkts++) = seg;
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@ -2925,6 +2971,11 @@ rxq_rehash(struct rte_eth_dev *dev, struct rxq *rxq)
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/* Number of descriptors and mbufs currently allocated. */
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desc_n = (tmpl.elts_n * (tmpl.sp ? MLX4_PMD_SGE_WR_N : 1));
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mbuf_n = desc_n;
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/* Toggle RX checksum offload if hardware supports it. */
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if (priv->hw_csum) {
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tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
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rxq->csum = tmpl.csum;
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}
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/* Enable scattered packets support for this queue if necessary. */
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if ((dev->data->dev_conf.rxmode.jumbo_frame) &&
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(dev->data->dev_conf.rxmode.max_rx_pkt_len >
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@ -3146,6 +3197,9 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,
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rte_pktmbuf_tailroom(buf)) == tmpl.mb_len);
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assert(rte_pktmbuf_headroom(buf) == RTE_PKTMBUF_HEADROOM);
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rte_pktmbuf_free(buf);
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/* Toggle RX checksum offload if hardware supports it. */
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if (priv->hw_csum)
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tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
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/* Enable scattered packets support for this queue if necessary. */
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if ((dev->data->dev_conf.rxmode.jumbo_frame) &&
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(dev->data->dev_conf.rxmode.max_rx_pkt_len >
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@ -3643,6 +3697,18 @@ mlx4_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
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info->max_rx_queues = max;
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info->max_tx_queues = max;
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info->max_mac_addrs = elemof(priv->mac);
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info->rx_offload_capa =
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(priv->hw_csum ?
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(DEV_RX_OFFLOAD_IPV4_CKSUM |
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DEV_RX_OFFLOAD_UDP_CKSUM |
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DEV_RX_OFFLOAD_TCP_CKSUM) :
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0);
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info->tx_offload_capa =
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(priv->hw_csum ?
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(DEV_TX_OFFLOAD_IPV4_CKSUM |
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DEV_TX_OFFLOAD_UDP_CKSUM |
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DEV_TX_OFFLOAD_TCP_CKSUM) :
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0);
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priv_unlock(priv);
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}
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@ -4683,6 +4749,14 @@ mlx4_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
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exp_device_attr.max_rss_tbl_sz);
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#endif /* RSS_SUPPORT */
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priv->hw_csum =
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((exp_device_attr.exp_device_cap_flags &
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IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) &&
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(exp_device_attr.exp_device_cap_flags &
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IBV_EXP_DEVICE_RX_CSUM_IP_PKT));
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DEBUG("checksum offloading is %ssupported",
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(priv->hw_csum ? "" : "not "));
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#ifdef INLINE_RECV
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priv->inl_recv_size = mlx4_getenv_int("MLX4_INLINE_RECV_SIZE");
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