i40e: support ieee1588 functions for device time
Add additional functions to support the existing IEEE1588 functionality and to enable getting, setting and adjusting the device time. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com> Reviewed-by: John McNamara <john.mcnamara@intel.com>
This commit is contained in:
Pablo de Lara
Thomas Monjalon
parent
9c857bf6be
commit
f3a4e40eca
@ -125,11 +125,13 @@
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(1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
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(1UL << RTE_ETH_FLOW_L2_PAYLOAD))
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#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
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#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
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#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
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#define I40E_PRTTSYN_TSYNENA 0x80000000
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#define I40E_PRTTSYN_TSYNTYPE 0x0e000000
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/* Additional timesync values. */
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#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
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#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
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#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
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#define I40E_PRTTSYN_TSYNENA 0x80000000
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#define I40E_PRTTSYN_TSYNTYPE 0x0e000000
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#define I40E_CYCLECOUNTER_MASK 0xffffffffffffffff
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#define I40E_MAX_PERCENT 100
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#define I40E_DEFAULT_DCB_APP_NUM 1
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@ -399,11 +401,20 @@ static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp);
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static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
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static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
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static int i40e_timesync_read_time(struct rte_eth_dev *dev,
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struct timespec *timestamp);
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static int i40e_timesync_write_time(struct rte_eth_dev *dev,
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const struct timespec *timestamp);
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static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
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uint16_t queue_id);
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static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
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uint16_t queue_id);
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static const struct rte_pci_id pci_id_i40e_map[] = {
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#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
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#include "rte_pci_dev_ids.h"
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@ -468,6 +479,9 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {
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.timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
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.timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
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.get_dcb_info = i40e_dev_get_dcb_info,
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.timesync_adjust_time = i40e_timesync_adjust_time,
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.timesync_read_time = i40e_timesync_read_time,
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.timesync_write_time = i40e_timesync_write_time,
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};
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/* store statistics names and its offset in stats structure */
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@ -7761,17 +7775,61 @@ i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
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return 0;
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}
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static int
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i40e_timesync_enable(struct rte_eth_dev *dev)
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static uint64_t
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i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
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{
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struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct rte_eth_link *link = &dev->data->dev_link;
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uint32_t tsync_ctl_l;
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uint32_t tsync_ctl_h;
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uint64_t systim_cycles;
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systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
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systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
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<< 32;
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return systim_cycles;
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}
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static uint64_t
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i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
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{
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struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t rx_tstamp;
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rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
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rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
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<< 32;
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return rx_tstamp;
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}
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static uint64_t
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i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
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{
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struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t tx_tstamp;
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tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
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tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
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<< 32;
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return tx_tstamp;
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}
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static void
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i40e_start_timecounters(struct rte_eth_dev *dev)
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{
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struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct i40e_adapter *adapter =
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(struct i40e_adapter *)dev->data->dev_private;
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struct rte_eth_link link;
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uint32_t tsync_inc_l;
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uint32_t tsync_inc_h;
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switch (link->link_speed) {
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/* Get current link speed. */
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memset(&link, 0, sizeof(link));
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i40e_dev_link_update(dev, 1);
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rte_i40e_dev_atomic_read_link_status(dev, &link);
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switch (link.link_speed) {
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case ETH_LINK_SPEED_40G:
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tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
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tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
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@ -7789,19 +7847,95 @@ i40e_timesync_enable(struct rte_eth_dev *dev)
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tsync_inc_h = 0x0;
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}
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/* Clear timesync registers. */
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I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
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I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
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I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
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I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
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I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
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I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
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I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
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/* Set the timesync increment value. */
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I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
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I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
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memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
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memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
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memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
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adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
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adapter->systime_tc.cc_shift = 0;
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adapter->systime_tc.nsec_mask = 0;
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adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
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adapter->rx_tstamp_tc.cc_shift = 0;
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adapter->rx_tstamp_tc.nsec_mask = 0;
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adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
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adapter->tx_tstamp_tc.cc_shift = 0;
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adapter->tx_tstamp_tc.nsec_mask = 0;
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}
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static int
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i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
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{
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struct i40e_adapter *adapter =
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(struct i40e_adapter *)dev->data->dev_private;
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adapter->systime_tc.nsec += delta;
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adapter->rx_tstamp_tc.nsec += delta;
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adapter->tx_tstamp_tc.nsec += delta;
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return 0;
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}
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static int
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i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
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{
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uint64_t ns;
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struct i40e_adapter *adapter =
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(struct i40e_adapter *)dev->data->dev_private;
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ns = rte_timespec_to_ns(ts);
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/* Set the timecounters to a new value. */
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adapter->systime_tc.nsec = ns;
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adapter->rx_tstamp_tc.nsec = ns;
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adapter->tx_tstamp_tc.nsec = ns;
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return 0;
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}
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static int
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i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
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{
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uint64_t ns, systime_cycles;
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struct i40e_adapter *adapter =
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(struct i40e_adapter *)dev->data->dev_private;
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systime_cycles = i40e_read_systime_cyclecounter(dev);
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ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
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*ts = rte_ns_to_timespec(ns);
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return 0;
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}
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static int
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i40e_timesync_enable(struct rte_eth_dev *dev)
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{
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struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t tsync_ctl_l;
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uint32_t tsync_ctl_h;
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/* Stop the timesync system time. */
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I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
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I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
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/* Reset the timesync system time value. */
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I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
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I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
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i40e_start_timecounters(dev);
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/* Clear timesync registers. */
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I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
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I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
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I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
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I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
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I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
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I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
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/* Enable timestamping of PTP packets. */
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tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
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tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
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@ -7833,7 +7967,7 @@ i40e_timesync_disable(struct rte_eth_dev *dev)
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I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
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I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
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/* Set the timesync increment value. */
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/* Reset the timesync increment value. */
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I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
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I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
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@ -7845,22 +7979,23 @@ i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp, uint32_t flags)
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{
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struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct i40e_adapter *adapter =
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(struct i40e_adapter *)dev->data->dev_private;
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uint32_t sync_status;
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uint32_t rx_stmpl;
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uint32_t rx_stmph;
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uint32_t index = flags & 0x03;
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uint64_t rx_tstamp_cycles;
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uint64_t ns;
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sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
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if ((sync_status & (1 << index)) == 0)
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return -EINVAL;
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rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
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rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
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rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
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ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
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*timestamp = rte_ns_to_timespec(ns);
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timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
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timestamp->tv_nsec = 0;
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return 0;
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return 0;
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}
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static int
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@ -7868,21 +8003,22 @@ i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp)
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{
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struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct i40e_adapter *adapter =
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(struct i40e_adapter *)dev->data->dev_private;
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uint32_t sync_status;
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uint32_t tx_stmpl;
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uint32_t tx_stmph;
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uint64_t tx_tstamp_cycles;
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uint64_t ns;
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sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
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if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
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return -EINVAL;
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tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
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tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
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tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
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ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
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*timestamp = rte_ns_to_timespec(ns);
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timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
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timestamp->tv_nsec = 0;
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return 0;
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return 0;
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}
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/*
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@ -35,6 +35,7 @@
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#define _I40E_ETHDEV_H_
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#include <rte_eth_ctrl.h>
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#include <rte_time.h>
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#define I40E_VLAN_TAG_SIZE 4
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@ -516,11 +517,16 @@ struct i40e_adapter {
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struct i40e_vf vf;
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};
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/* for vector PMD */
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/* For vector PMD */
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bool rx_bulk_alloc_allowed;
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bool rx_vec_allowed;
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bool tx_simple_allowed;
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bool tx_vec_allowed;
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/* For PTP */
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struct rte_timecounter systime_tc;
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struct rte_timecounter rx_tstamp_tc;
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struct rte_timecounter tx_tstamp_tc;
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};
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int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
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