event/dlb2: add infos get and configure
Add support for configuring the DLB2 hardware. In particular, this patch configures the DLB2 hardware's scheduling domain, such that it is provisioned with the requested number of ports and queues, provided sufficient resources are available. Individual queues and ports are configured later in port setup and eventdev start. Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com> Reviewed-by: Gage Eads <gage.eads@intel.com>
This commit is contained in:
Timothy McDaniel
Jerin Jacob
parent
e88753dcc1
commit
f3cad285bb
@ -32,9 +32,125 @@ detailed understanding of the hardware, but these details are important when
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writing high-performance code. This section describes the places where the
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eventdev API and DLB2 misalign.
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Scheduling Domain Configuration
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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There are 32 scheduling domainis the DLB2.
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When one is configured, it allocates load-balanced and
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directed queues, ports, credits, and other hardware resources. Some
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resource allocations are user-controlled -- the number of queues, for example
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-- and others, like credit pools (one directed and one load-balanced pool per
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scheduling domain), are not.
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The DLB2 is a closed system eventdev, and as such the ``nb_events_limit`` device
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setup argument and the per-port ``new_event_threshold`` argument apply as
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defined in the eventdev header file. The limit is applied to all enqueues,
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regardless of whether it will consume a directed or load-balanced credit.
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Load-balanced and Directed Ports
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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DLB2 ports come in two flavors: load-balanced and directed. The eventdev API
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does not have the same concept, but it has a similar one: ports and queues that
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are singly-linked (i.e. linked to a single queue or port, respectively).
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The ``rte_event_dev_info_get()`` function reports the number of available
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event ports and queues (among other things). For the DLB2 PMD, max_event_ports
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and max_event_queues report the number of available load-balanced ports and
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queues, and max_single_link_event_port_queue_pairs reports the number of
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available directed ports and queues.
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When a scheduling domain is created in ``rte_event_dev_configure()``, the user
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specifies ``nb_event_ports`` and ``nb_single_link_event_port_queues``, which
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control the total number of ports (load-balanced and directed) and the number
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of directed ports. Hence, the number of requested load-balanced ports is
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``nb_event_ports - nb_single_link_event_ports``. The ``nb_event_queues`` field
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specifies the total number of queues (load-balanced and directed). The number
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of directed queues comes from ``nb_single_link_event_port_queues``, since
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directed ports and queues come in pairs.
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When a port is setup, the ``RTE_EVENT_PORT_CFG_SINGLE_LINK`` flag determines
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whether it should be configured as a directed (the flag is set) or a
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load-balanced (the flag is unset) port. Similarly, the
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``RTE_EVENT_QUEUE_CFG_SINGLE_LINK`` queue configuration flag controls
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whether it is a directed or load-balanced queue.
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Load-balanced ports can only be linked to load-balanced queues, and directed
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ports can only be linked to directed queues. Furthermore, directed ports can
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only be linked to a single directed queue (and vice versa), and that link
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cannot change after the eventdev is started.
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The eventdev API does not have a directed scheduling type. To support directed
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traffic, the dlb PMD detects when an event is being sent to a directed queue
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and overrides its scheduling type. Note that the originally selected scheduling
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type (atomic, ordered, or parallel) is not preserved, and an event's sched_type
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will be set to ``RTE_SCHED_TYPE_ATOMIC`` when it is dequeued from a directed
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port.
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Flow ID
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~~~~~~~
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The flow ID field is preserved in the event when it is scheduled in the
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DLB2.
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Reconfiguration
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~~~~~~~~~~~~~~~
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The Eventdev API allows one to reconfigure a device, its ports, and its queues
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by first stopping the device, calling the configuration function(s), then
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restarting the device. The DLB2 does not support configuring an individual queue
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or port without first reconfiguring the entire device, however, so there are
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certain reconfiguration sequences that are valid in the eventdev API but not
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supported by the PMD.
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Specifically, the PMD supports the following configuration sequence:
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1. Configure and start the device
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2. Stop the device
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3. (Optional) Reconfigure the device
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4. (Optional) If step 3 is run:
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a. Setup queue(s). The reconfigured queue(s) lose their previous port links.
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b. The reconfigured port(s) lose their previous queue links.
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5. (Optional, only if steps 4a and 4b are run) Link port(s) to queue(s)
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6. Restart the device. If the device is reconfigured in step 3 but one or more
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of its ports or queues are not, the PMD will apply their previous
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configuration (including port->queue links) at this time.
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The PMD does not support the following configuration sequences:
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1. Configure and start the device
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2. Stop the device
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3. Setup queue or setup port
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4. Start the device
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This sequence is not supported because the event device must be reconfigured
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before its ports or queues can be.
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Atomic Inflights Allocation
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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In the last stage prior to scheduling an atomic event to a CQ, DLB2 holds the
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inflight event in a temporary buffer that is divided among load-balanced
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queues. If a queue's atomic buffer storage fills up, this can result in
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head-of-line-blocking. For example:
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- An LDB queue allocated N atomic buffer entries
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- All N entries are filled with events from flow X, which is pinned to CQ 0.
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Until CQ 0 releases 1+ events, no other atomic flows for that LDB queue can be
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scheduled. The likelihood of this case depends on the eventdev configuration,
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traffic behavior, event processing latency, potential for a worker to be
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interrupted or otherwise delayed, etc.
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By default, the PMD allocates 16 buffer entries for each load-balanced queue,
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which provides an even division across all 128 queues but potentially wastes
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buffer space (e.g. if not all queues are used, or aren't used for atomic
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scheduling).
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The PMD provides a dev arg to override the default per-queue allocation. To
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increase a vdev's per-queue atomic-inflight allocation to (for example) 64:
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.. code-block:: console
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--vdev=dlb1_event,atm_inflights=64
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@ -85,6 +85,25 @@ dlb2_get_queue_depth(struct dlb2_eventdev *dlb2,
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return 0;
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}
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static void
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dlb2_free_qe_mem(struct dlb2_port *qm_port)
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{
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if (qm_port == NULL)
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return;
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rte_free(qm_port->qe4);
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qm_port->qe4 = NULL;
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rte_free(qm_port->int_arm_qe);
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qm_port->int_arm_qe = NULL;
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rte_free(qm_port->consume_qe);
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qm_port->consume_qe = NULL;
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rte_memzone_free(dlb2_port[qm_port->id][PORT_TYPE(qm_port)].mz);
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dlb2_port[qm_port->id][PORT_TYPE(qm_port)].mz = NULL;
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}
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/* override defaults with value(s) provided on command line */
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static void
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dlb2_init_queue_depth_thresholds(struct dlb2_eventdev *dlb2,
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@ -349,11 +368,305 @@ set_qid_depth_thresh(const char *key __rte_unused,
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return 0;
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}
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static void
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dlb2_eventdev_info_get(struct rte_eventdev *dev,
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struct rte_event_dev_info *dev_info)
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{
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struct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);
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int ret;
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ret = dlb2_hw_query_resources(dlb2);
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if (ret) {
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const struct rte_eventdev_data *data = dev->data;
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DLB2_LOG_ERR("get resources err=%d, devid=%d\n",
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ret, data->dev_id);
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/* fn is void, so fall through and return values set up in
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* probe
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*/
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}
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/* Add num resources currently owned by this domain.
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* These would become available if the scheduling domain were reset due
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* to the application recalling eventdev_configure to *reconfigure* the
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* domain.
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*/
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evdev_dlb2_default_info.max_event_ports += dlb2->num_ldb_ports;
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evdev_dlb2_default_info.max_event_queues += dlb2->num_ldb_queues;
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evdev_dlb2_default_info.max_num_events += dlb2->max_ldb_credits;
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evdev_dlb2_default_info.max_event_queues =
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RTE_MIN(evdev_dlb2_default_info.max_event_queues,
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RTE_EVENT_MAX_QUEUES_PER_DEV);
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evdev_dlb2_default_info.max_num_events =
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RTE_MIN(evdev_dlb2_default_info.max_num_events,
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dlb2->max_num_events_override);
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*dev_info = evdev_dlb2_default_info;
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}
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static int
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dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,
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const struct dlb2_hw_rsrcs *resources_asked)
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{
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int ret = 0;
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struct dlb2_create_sched_domain_args *cfg;
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if (resources_asked == NULL) {
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DLB2_LOG_ERR("dlb2: dlb2_create NULL parameter\n");
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ret = EINVAL;
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goto error_exit;
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}
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/* Map generic qm resources to dlb2 resources */
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cfg = &handle->cfg.resources;
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/* DIR ports and queues */
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cfg->num_dir_ports = resources_asked->num_dir_ports;
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cfg->num_dir_credits = resources_asked->num_dir_credits;
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/* LDB queues */
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cfg->num_ldb_queues = resources_asked->num_ldb_queues;
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/* LDB ports */
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cfg->cos_strict = 0; /* Best effort */
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cfg->num_cos_ldb_ports[0] = 0;
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cfg->num_cos_ldb_ports[1] = 0;
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cfg->num_cos_ldb_ports[2] = 0;
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cfg->num_cos_ldb_ports[3] = 0;
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switch (handle->cos_id) {
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case DLB2_COS_0:
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cfg->num_ldb_ports = 0; /* no don't care ports */
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cfg->num_cos_ldb_ports[0] =
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resources_asked->num_ldb_ports;
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break;
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case DLB2_COS_1:
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cfg->num_ldb_ports = 0; /* no don't care ports */
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cfg->num_cos_ldb_ports[1] = resources_asked->num_ldb_ports;
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break;
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case DLB2_COS_2:
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cfg->num_ldb_ports = 0; /* no don't care ports */
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cfg->num_cos_ldb_ports[2] = resources_asked->num_ldb_ports;
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break;
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case DLB2_COS_3:
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cfg->num_ldb_ports = 0; /* no don't care ports */
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cfg->num_cos_ldb_ports[3] =
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resources_asked->num_ldb_ports;
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break;
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case DLB2_COS_DEFAULT:
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/* all ldb ports are don't care ports from a cos perspective */
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cfg->num_ldb_ports =
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resources_asked->num_ldb_ports;
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break;
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}
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cfg->num_ldb_credits =
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resources_asked->num_ldb_credits;
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cfg->num_atomic_inflights =
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DLB2_NUM_ATOMIC_INFLIGHTS_PER_QUEUE *
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cfg->num_ldb_queues;
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cfg->num_hist_list_entries = resources_asked->num_ldb_ports *
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DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;
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DLB2_LOG_DBG("sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, ldb_credits=%d, dir_credits=%d\n",
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cfg->num_ldb_queues,
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resources_asked->num_ldb_ports,
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cfg->num_dir_ports,
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cfg->num_atomic_inflights,
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cfg->num_hist_list_entries,
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cfg->num_ldb_credits,
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cfg->num_dir_credits);
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/* Configure the QM */
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ret = dlb2_iface_sched_domain_create(handle, cfg);
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if (ret < 0) {
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DLB2_LOG_ERR("dlb2: domain create failed, ret = %d, extra status: %s\n",
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ret,
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dlb2_error_strings[cfg->response.status]);
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goto error_exit;
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}
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handle->domain_id = cfg->response.id;
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handle->cfg.configured = true;
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error_exit:
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return ret;
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}
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static void
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dlb2_hw_reset_sched_domain(const struct rte_eventdev *dev, bool reconfig)
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{
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struct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);
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enum dlb2_configuration_state config_state;
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int i, j;
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dlb2_iface_domain_reset(dlb2);
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/* Free all dynamically allocated port memory */
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for (i = 0; i < dlb2->num_ports; i++)
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dlb2_free_qe_mem(&dlb2->ev_ports[i].qm_port);
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/* If reconfiguring, mark the device's queues and ports as "previously
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* configured." If the user doesn't reconfigure them, the PMD will
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* reapply their previous configuration when the device is started.
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*/
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config_state = (reconfig) ? DLB2_PREV_CONFIGURED :
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DLB2_NOT_CONFIGURED;
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for (i = 0; i < dlb2->num_ports; i++) {
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dlb2->ev_ports[i].qm_port.config_state = config_state;
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/* Reset setup_done so ports can be reconfigured */
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dlb2->ev_ports[i].setup_done = false;
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for (j = 0; j < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; j++)
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dlb2->ev_ports[i].link[j].mapped = false;
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}
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for (i = 0; i < dlb2->num_queues; i++)
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dlb2->ev_queues[i].qm_queue.config_state = config_state;
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for (i = 0; i < DLB2_MAX_NUM_QUEUES; i++)
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dlb2->ev_queues[i].setup_done = false;
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dlb2->num_ports = 0;
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dlb2->num_ldb_ports = 0;
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dlb2->num_dir_ports = 0;
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dlb2->num_queues = 0;
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dlb2->num_ldb_queues = 0;
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dlb2->num_dir_queues = 0;
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dlb2->configured = false;
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}
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/* Note: 1 QM instance per QM device, QM instance/device == event device */
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static int
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dlb2_eventdev_configure(const struct rte_eventdev *dev)
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{
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struct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);
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struct dlb2_hw_dev *handle = &dlb2->qm_instance;
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struct dlb2_hw_rsrcs *rsrcs = &handle->info.hw_rsrc_max;
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const struct rte_eventdev_data *data = dev->data;
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const struct rte_event_dev_config *config = &data->dev_conf;
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int ret;
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/* If this eventdev is already configured, we must release the current
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* scheduling domain before attempting to configure a new one.
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*/
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if (dlb2->configured) {
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dlb2_hw_reset_sched_domain(dev, true);
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ret = dlb2_hw_query_resources(dlb2);
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if (ret) {
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DLB2_LOG_ERR("get resources err=%d, devid=%d\n",
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ret, data->dev_id);
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return ret;
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}
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}
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if (config->nb_event_queues > rsrcs->num_queues) {
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DLB2_LOG_ERR("nb_event_queues parameter (%d) exceeds the QM device's capabilities (%d).\n",
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config->nb_event_queues,
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rsrcs->num_queues);
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return -EINVAL;
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}
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if (config->nb_event_ports > (rsrcs->num_ldb_ports
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+ rsrcs->num_dir_ports)) {
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DLB2_LOG_ERR("nb_event_ports parameter (%d) exceeds the QM device's capabilities (%d).\n",
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config->nb_event_ports,
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(rsrcs->num_ldb_ports + rsrcs->num_dir_ports));
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return -EINVAL;
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}
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if (config->nb_events_limit > rsrcs->nb_events_limit) {
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DLB2_LOG_ERR("nb_events_limit parameter (%d) exceeds the QM device's capabilities (%d).\n",
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config->nb_events_limit,
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rsrcs->nb_events_limit);
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return -EINVAL;
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}
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if (config->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
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dlb2->global_dequeue_wait = false;
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else {
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uint32_t timeout32;
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dlb2->global_dequeue_wait = true;
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/* note size mismatch of timeout vals in eventdev lib. */
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timeout32 = config->dequeue_timeout_ns;
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dlb2->global_dequeue_wait_ticks =
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timeout32 * (rte_get_timer_hz() / 1E9);
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}
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/* Does this platform support umonitor/umwait? */
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if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WAITPKG)) {
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if (RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE != 0 &&
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RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE != 1) {
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DLB2_LOG_ERR("invalid value (%d) for RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE, must be 0 or 1.\n",
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RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE);
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return -EINVAL;
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}
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dlb2->umwait_allowed = true;
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}
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rsrcs->num_dir_ports = config->nb_single_link_event_port_queues;
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rsrcs->num_ldb_ports = config->nb_event_ports - rsrcs->num_dir_ports;
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/* 1 dir queue per dir port */
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rsrcs->num_ldb_queues = config->nb_event_queues - rsrcs->num_dir_ports;
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/* Scale down nb_events_limit by 4 for directed credits, since there
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* are 4x as many load-balanced credits.
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*/
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rsrcs->num_ldb_credits = 0;
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rsrcs->num_dir_credits = 0;
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if (rsrcs->num_ldb_queues)
|
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rsrcs->num_ldb_credits = config->nb_events_limit;
|
||||
if (rsrcs->num_dir_ports)
|
||||
rsrcs->num_dir_credits = config->nb_events_limit / 4;
|
||||
if (dlb2->num_dir_credits_override != -1)
|
||||
rsrcs->num_dir_credits = dlb2->num_dir_credits_override;
|
||||
|
||||
if (dlb2_hw_create_sched_domain(handle, rsrcs) < 0) {
|
||||
DLB2_LOG_ERR("dlb2_hw_create_sched_domain failed\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
dlb2->new_event_limit = config->nb_events_limit;
|
||||
__atomic_store_n(&dlb2->inflights, 0, __ATOMIC_SEQ_CST);
|
||||
|
||||
/* Save number of ports/queues for this event dev */
|
||||
dlb2->num_ports = config->nb_event_ports;
|
||||
dlb2->num_queues = config->nb_event_queues;
|
||||
dlb2->num_dir_ports = rsrcs->num_dir_ports;
|
||||
dlb2->num_ldb_ports = dlb2->num_ports - dlb2->num_dir_ports;
|
||||
dlb2->num_ldb_queues = dlb2->num_queues - dlb2->num_dir_ports;
|
||||
dlb2->num_dir_queues = dlb2->num_dir_ports;
|
||||
dlb2->ldb_credit_pool = rsrcs->num_ldb_credits;
|
||||
dlb2->max_ldb_credits = rsrcs->num_ldb_credits;
|
||||
dlb2->dir_credit_pool = rsrcs->num_dir_credits;
|
||||
dlb2->max_dir_credits = rsrcs->num_dir_credits;
|
||||
|
||||
dlb2->configured = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
dlb2_entry_points_init(struct rte_eventdev *dev)
|
||||
{
|
||||
/* Expose PMD's eventdev interface */
|
||||
static struct rte_eventdev_ops dlb2_eventdev_entry_ops = {
|
||||
.dev_infos_get = dlb2_eventdev_info_get,
|
||||
.dev_configure = dlb2_eventdev_configure,
|
||||
.dump = dlb2_eventdev_dump,
|
||||
.xstats_get = dlb2_eventdev_xstats_get,
|
||||
.xstats_get_names = dlb2_eventdev_xstats_get_names,
|
||||
|
||||
@ -26,3 +26,8 @@ int (*dlb2_iface_get_cq_poll_mode)(struct dlb2_hw_dev *handle,
|
||||
|
||||
int (*dlb2_iface_get_num_resources)(struct dlb2_hw_dev *handle,
|
||||
struct dlb2_get_num_resources_args *rsrcs);
|
||||
|
||||
int (*dlb2_iface_sched_domain_create)(struct dlb2_hw_dev *handle,
|
||||
struct dlb2_create_sched_domain_args *args);
|
||||
|
||||
void (*dlb2_iface_domain_reset)(struct dlb2_eventdev *dlb2);
|
||||
|
||||
@ -26,4 +26,8 @@ extern int (*dlb2_iface_get_cq_poll_mode)(struct dlb2_hw_dev *handle,
|
||||
extern int (*dlb2_iface_get_num_resources)(struct dlb2_hw_dev *handle,
|
||||
struct dlb2_get_num_resources_args *rsrcs);
|
||||
|
||||
extern int (*dlb2_iface_sched_domain_create)(struct dlb2_hw_dev *handle,
|
||||
struct dlb2_create_sched_domain_args *args);
|
||||
|
||||
extern void (*dlb2_iface_domain_reset)(struct dlb2_eventdev *dlb2);
|
||||
#endif /* _DLB2_IFACE_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -598,3 +598,18 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
dlb2_pf_create_sched_domain(struct dlb2_hw *hw,
|
||||
struct dlb2_create_sched_domain_args *args,
|
||||
struct dlb2_cmd_response *resp)
|
||||
{
|
||||
return dlb2_hw_create_sched_domain(hw, args, resp, NOT_VF_REQ,
|
||||
PF_ID_ZERO);
|
||||
}
|
||||
|
||||
int
|
||||
dlb2_pf_reset_domain(struct dlb2_hw *hw, u32 id)
|
||||
{
|
||||
return dlb2_reset_domain(hw, id, NOT_VF_REQ, PF_ID_ZERO);
|
||||
}
|
||||
|
||||
@ -108,15 +108,59 @@ dlb2_pf_get_cq_poll_mode(struct dlb2_hw_dev *handle,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
dlb2_pf_sched_domain_create(struct dlb2_hw_dev *handle,
|
||||
struct dlb2_create_sched_domain_args *arg)
|
||||
{
|
||||
struct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;
|
||||
struct dlb2_cmd_response response = {0};
|
||||
int ret;
|
||||
|
||||
DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__);
|
||||
|
||||
if (dlb2_dev->domain_reset_failed) {
|
||||
response.status = DLB2_ST_DOMAIN_RESET_FAILED;
|
||||
ret = -EINVAL;
|
||||
goto done;
|
||||
}
|
||||
|
||||
ret = dlb2_pf_create_sched_domain(&dlb2_dev->hw, arg, &response);
|
||||
if (ret)
|
||||
goto done;
|
||||
|
||||
done:
|
||||
|
||||
arg->response = response;
|
||||
|
||||
DLB2_INFO(dev->dlb2_device, "Exiting %s() with ret=%d\n",
|
||||
__func__, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
dlb2_pf_domain_reset(struct dlb2_eventdev *dlb2)
|
||||
{
|
||||
struct dlb2_dev *dlb2_dev;
|
||||
int ret;
|
||||
|
||||
dlb2_dev = (struct dlb2_dev *)dlb2->qm_instance.pf_dev;
|
||||
ret = dlb2_pf_reset_domain(&dlb2_dev->hw, dlb2->qm_instance.domain_id);
|
||||
if (ret)
|
||||
DLB2_LOG_ERR("dlb2_pf_reset_domain err %d", ret);
|
||||
}
|
||||
|
||||
static void
|
||||
dlb2_pf_iface_fn_ptrs_init(void)
|
||||
{
|
||||
dlb2_iface_low_level_io_init = dlb2_pf_low_level_io_init;
|
||||
dlb2_iface_open = dlb2_pf_open;
|
||||
dlb2_iface_domain_reset = dlb2_pf_domain_reset;
|
||||
dlb2_iface_get_device_version = dlb2_pf_get_device_version;
|
||||
dlb2_iface_hardware_init = dlb2_pf_hardware_init;
|
||||
dlb2_iface_get_num_resources = dlb2_pf_get_num_resources;
|
||||
dlb2_iface_get_cq_poll_mode = dlb2_pf_get_cq_poll_mode;
|
||||
dlb2_iface_sched_domain_create = dlb2_pf_sched_domain_create;
|
||||
}
|
||||
|
||||
/* PCI DEV HOOKS */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user