net/txgbe: support OEM customized LED
Support to configure LED in firmware. Driver commands firmware to turn the LED on and off. And OEM customize their LED solutions in firmware. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
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@ -45,6 +45,7 @@ FW version = Y
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EEPROM dump = Y
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Module EEPROM dump = Y
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Registers dump = Y
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LED = Y
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Multiprocess aware = Y
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Linux = Y
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ARMv8 = Y
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@ -111,6 +111,10 @@ New Features
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- YT8521S PHY connects to SFP
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* Added LED OEM support.
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* **Updated Wangxun txgbe driver.**
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* Added LED OEM support.
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* **Updated Marvell cnxk crypto PMD.**
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* Added SHA256-HMAC support in lookaside protocol (IPsec) for CN10K.
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@ -529,12 +529,9 @@ s32 txgbe_led_on(struct txgbe_hw *hw, u32 index)
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DEBUGFUNC("txgbe_led_on");
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if (index > 4)
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return TXGBE_ERR_PARAM;
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/* To turn on the LED, set mode to ON. */
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led_reg |= TXGBE_LEDCTL_SEL(index);
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led_reg |= TXGBE_LEDCTL_ORD(index);
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led_reg |= index << TXGBE_LEDCTL_ORD_SHIFT;
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led_reg |= index;
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wr32(hw, TXGBE_LEDCTL, led_reg);
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txgbe_flush(hw);
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@ -552,12 +549,9 @@ s32 txgbe_led_off(struct txgbe_hw *hw, u32 index)
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DEBUGFUNC("txgbe_led_off");
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if (index > 4)
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return TXGBE_ERR_PARAM;
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/* To turn off the LED, set mode to OFF. */
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led_reg &= ~(TXGBE_LEDCTL_SEL(index));
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led_reg &= ~(TXGBE_LEDCTL_ORD(index));
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led_reg &= ~(index << TXGBE_LEDCTL_ORD_SHIFT);
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led_reg |= index;
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wr32(hw, TXGBE_LEDCTL, led_reg);
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txgbe_flush(hw);
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@ -3054,6 +3048,10 @@ void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
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if (txgbe_check_reset_blocked(hw))
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return;
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if (txgbe_close_notify(hw))
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txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_LEDCTL_10G |
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TXGBE_LEDCTL_1G | TXGBE_LEDCTL_ACTIVE);
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/* Disable Tx laser; allow 100us to go dark per spec */
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esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
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wr32(hw, TXGBE_GPIODATA, esdp_reg);
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@ -3073,6 +3071,9 @@ void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
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{
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u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
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if (txgbe_open_notify(hw))
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wr32(hw, TXGBE_LEDCTL, 0);
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/* Enable Tx laser; allow 100ms to light up */
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esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
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wr32(hw, TXGBE_GPIODATA, esdp_reg);
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@ -82,6 +82,11 @@ txgbe_hic_unlocked(struct txgbe_hw *hw, u32 *buffer, u32 length, u32 timeout)
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return TXGBE_ERR_HOST_INTERFACE_COMMAND;
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}
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if ((rd32(hw, TXGBE_MNGMBX) & 0xff0000) >> 16 == 0x80) {
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DEBUGOUT("It's unknown command.\n");
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return TXGBE_ERR_MNG_ACCESS_FAILED;
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}
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return 0;
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}
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@ -262,6 +267,70 @@ s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len)
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return err;
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}
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s32 txgbe_close_notify(struct txgbe_hw *hw)
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{
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u32 tmp;
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s32 status;
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struct txgbe_hic_write_shadow_ram buffer;
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DEBUGFUNC("txgbe_close_notify");
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buffer.hdr.req.cmd = FW_DW_CLOSE_NOTIFY;
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buffer.hdr.req.buf_lenh = 0;
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buffer.hdr.req.buf_lenl = 0;
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buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
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/* one word */
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buffer.length = 0;
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buffer.address = 0;
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status = txgbe_host_interface_command(hw, (u32 *)&buffer,
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sizeof(buffer),
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TXGBE_HI_COMMAND_TIMEOUT, false);
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if (status)
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return status;
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tmp = rd32(hw, TXGBE_MNGSWSYNC);
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if (tmp == TXGBE_CHECKSUM_CAP_ST_PASS)
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status = 0;
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else
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status = TXGBE_ERR_EEPROM_CHECKSUM;
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return status;
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}
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s32 txgbe_open_notify(struct txgbe_hw *hw)
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{
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u32 tmp;
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s32 status;
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struct txgbe_hic_write_shadow_ram buffer;
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DEBUGFUNC("txgbe_open_notify");
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buffer.hdr.req.cmd = FW_DW_OPEN_NOTIFY;
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buffer.hdr.req.buf_lenh = 0;
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buffer.hdr.req.buf_lenl = 0;
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buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
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/* one word */
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buffer.length = 0;
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buffer.address = 0;
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status = txgbe_host_interface_command(hw, (u32 *)&buffer,
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sizeof(buffer),
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TXGBE_HI_COMMAND_TIMEOUT, false);
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if (status)
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return status;
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tmp = rd32(hw, TXGBE_MNGSWSYNC);
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if (tmp == TXGBE_CHECKSUM_CAP_ST_PASS)
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status = 0;
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else
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status = TXGBE_ERR_EEPROM_CHECKSUM;
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return status;
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}
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/**
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* txgbe_hic_set_drv_ver - Sends driver version to firmware
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* @hw: pointer to the HW structure
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@ -51,6 +51,11 @@
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#define FW_PHY_TOKEN_DELAY 5 /* milliseconds */
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#define FW_PHY_TOKEN_WAIT 5 /* seconds */
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#define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
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#define FW_DW_OPEN_NOTIFY 0xE9
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#define FW_DW_CLOSE_NOTIFY 0xEA
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#define TXGBE_CHECKSUM_CAP_ST_PASS 0x80658383
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#define TXGBE_CHECKSUM_CAP_ST_FAIL 0x70657376
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/* Host Interface Command Structures */
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struct txgbe_hic_hdr {
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@ -168,6 +173,8 @@ struct txgbe_hic_upg_verify {
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s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len);
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s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len);
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s32 txgbe_close_notify(struct txgbe_hw *hw);
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s32 txgbe_open_notify(struct txgbe_hw *hw);
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s32 txgbe_hic_set_drv_ver(struct txgbe_hw *hw, u8 maj, u8 min, u8 build,
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u8 ver, u16 len, const char *str);
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@ -302,11 +302,13 @@
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#define TXGBE_TEREDOPORT 0x01441C
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#define TXGBE_LEDCTL 0x014424
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#define TXGBE_LEDCTL_SEL_MASK MS(0, 0xFFFF)
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#define TXGBE_LEDCTL_SEL(s) MS((s), 0x1)
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#define TXGBE_LEDCTL_ORD_MASK MS(16, 0xFFFF)
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#define TXGBE_LEDCTL_ORD(s) MS(((s)+16), 0x1)
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/* s=UP(0),10G(1),1G(2),100M(3),BSY(4) */
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#define TXGBE_LEDCTL_ACTIVE (TXGBE_LEDCTL_SEL(4) | TXGBE_LEDCTL_ORD(4))
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#define TXGBE_LEDCTL_ORD_SHIFT 16
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#define TXGBE_LEDCTL_UP MS(0, 0x1)
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#define TXGBE_LEDCTL_10G MS(1, 0x1)
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#define TXGBE_LEDCTL_1G MS(2, 0x1)
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#define TXGBE_LEDCTL_100M MS(3, 0x1)
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#define TXGBE_LEDCTL_ACTIVE MS(4, 0x1)
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#define TXGBE_TAGTPID(i) (0x014430 + (i) * 4) /* 0-3 */
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#define TXGBE_TAGTPID_LSB_MASK MS(0, 0xFFFF)
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#define TXGBE_TAGTPID_LSB(v) LS(v, 0, 0xFFFF)
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@ -3162,7 +3162,7 @@ txgbe_dev_led_on(struct rte_eth_dev *dev)
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struct txgbe_hw *hw;
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hw = TXGBE_DEV_HW(dev);
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return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
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return txgbe_led_on(hw, TXGBE_LEDCTL_ACTIVE) == 0 ? 0 : -ENOTSUP;
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}
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static int
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@ -3171,7 +3171,7 @@ txgbe_dev_led_off(struct rte_eth_dev *dev)
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struct txgbe_hw *hw;
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hw = TXGBE_DEV_HW(dev);
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return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
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return txgbe_led_off(hw, TXGBE_LEDCTL_ACTIVE) == 0 ? 0 : -ENOTSUP;
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}
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static int
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