raw/ntb: support Intel Ice Lake
Add NTB device support (4th generation) for Intel Ice Lake platform. Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com>
This commit is contained in:
Xiaoyun Li
Thomas Monjalon
parent
6f2dc9c0b4
commit
f5057be340
@ -14,16 +14,16 @@ allocation for the peer to access and read/write allocated memory from peer.
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Also, the PMD allows to use doorbell registers to notify the peer and share
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some information by using scratchpad registers.
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BIOS setting on Intel Skylake
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-----------------------------
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BIOS setting on Intel Xeon
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--------------------------
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Intel Non-transparent Bridge needs special BIOS setting. Since the PMD only
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supports Intel Skylake platform, introduce BIOS setting here. The referencce
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is https://www.intel.com/content/dam/support/us/en/documents/server-products/Intel_Xeon_Processor_Scalable_Family_BIOS_User_Guide.pdf
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Intel Non-transparent Bridge needs special BIOS setting. The referencce for
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Skylake is https://www.intel.com/content/dam/support/us/en/documents/server-products/Intel_Xeon_Processor_Scalable_Family_BIOS_User_Guide.pdf
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- Set the needed PCIe port as NTB to NTB mode on both hosts.
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- Enable NTB bars and set bar size of bar 23 and bar 45 as 12-29 (2K-512M)
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on both hosts. Note that bar size on both hosts should be the same.
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- Enable NTB bars and set bar size of bar 23 and bar 45 as 12-29 (4K-512M)
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on both hosts (for Ice Lake, bar size can be set as 12-51, namely 4K-128PB).
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Note that bar size on both hosts should be the same.
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- Disable split bars for both hosts.
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- Set crosslink control override as DSD/USP on one host, USD/DSP on
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another host.
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@ -151,4 +151,4 @@ like the following:
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Limitation
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----------
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- This PMD only supports Intel Skylake platform.
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- This PMD only supports Intel Skylake and Ice Lake platforms.
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@ -80,6 +80,10 @@ New Features
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* Changed default link speed to unknown.
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* Added support for 200G link speed.
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* **Added Ice Lake (Gen4) support for Intel NTB.**
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Added NTB device support (4th generation) for Intel Ice Lake platform.
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* **Extended flow-perf application.**
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* Started supporting user order instead of bit mask:
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@ -25,6 +25,7 @@
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static const struct rte_pci_id pci_id_ntb_map[] = {
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{ RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_SKX) },
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{ RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_ICX) },
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{ .vendor_id = 0, /* sentinel */ },
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};
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@ -244,6 +245,9 @@ ntb_dev_intr_handler(void *param)
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hw->peer_dev_up = 0;
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return;
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}
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/* Clear other received doorbells. */
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(*hw->ntb_ops->db_clear)(dev, db_bits);
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}
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static int
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@ -1360,6 +1364,7 @@ ntb_init_hw(struct rte_rawdev *dev, struct rte_pci_device *pci_dev)
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switch (pci_dev->id.device_id) {
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case NTB_INTEL_DEV_ID_B2B_SKX:
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case NTB_INTEL_DEV_ID_B2B_ICX:
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hw->ntb_ops = &intel_ntb_ops;
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break;
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default:
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@ -18,6 +18,7 @@ extern int ntb_logtype;
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/* Device IDs */
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#define NTB_INTEL_DEV_ID_B2B_SKX 0x201C
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#define NTB_INTEL_DEV_ID_B2B_ICX 0x347E
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/* Reserved to app to use. */
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#define NTB_SPAD_USER "spad_user_"
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@ -25,17 +25,29 @@ static enum xeon_ntb_bar intel_ntb_bar[] = {
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XEON_NTB_BAR45,
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};
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static int
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intel_ntb_dev_init(const struct rte_rawdev *dev)
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static inline int
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is_gen3_ntb(const struct ntb_hw *hw)
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{
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struct ntb_hw *hw = dev->dev_private;
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uint8_t reg_val, bar;
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int ret, i;
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if (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_SKX)
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return 1;
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if (hw == NULL) {
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NTB_LOG(ERR, "Invalid device.");
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return -EINVAL;
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}
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return 0;
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}
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static inline int
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is_gen4_ntb(const struct ntb_hw *hw)
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{
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if (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_ICX)
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return 1;
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return 0;
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}
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static int
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intel_ntb3_check_ppd(struct ntb_hw *hw)
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{
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uint8_t reg_val;
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int ret;
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ret = rte_pci_read_config(hw->pci_dev, ®_val,
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sizeof(reg_val), XEON_PPD_OFFSET);
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@ -71,8 +83,65 @@ intel_ntb_dev_init(const struct rte_rawdev *dev)
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return -EINVAL;
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}
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return 0;
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}
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static int
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intel_ntb4_check_ppd(struct ntb_hw *hw)
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{
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uint32_t reg_val;
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reg_val = rte_read32(hw->hw_addr + XEON_GEN4_PPD1_OFFSET);
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/* Check connection topo type. Only support B2B. */
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switch (reg_val & XEON_GEN4_PPD_CONN_MASK) {
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case XEON_GEN4_PPD_CONN_B2B:
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NTB_LOG(INFO, "Topo B2B (back to back) is using.");
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break;
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default:
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NTB_LOG(ERR, "Not supported conn topo. Please use B2B.");
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return -EINVAL;
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}
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/* Check device type. */
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if (reg_val & XEON_GEN4_PPD_DEV_DSD) {
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NTB_LOG(INFO, "DSD, Downstream Device.");
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hw->topo = NTB_TOPO_B2B_DSD;
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} else {
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NTB_LOG(INFO, "USD, Upstream device.");
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hw->topo = NTB_TOPO_B2B_USD;
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}
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return 0;
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}
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static int
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intel_ntb_dev_init(const struct rte_rawdev *dev)
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{
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struct ntb_hw *hw = dev->dev_private;
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uint8_t bar;
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int ret, i;
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if (hw == NULL) {
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NTB_LOG(ERR, "Invalid device.");
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return -EINVAL;
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}
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hw->hw_addr = (char *)hw->pci_dev->mem_resource[0].addr;
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if (is_gen3_ntb(hw))
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ret = intel_ntb3_check_ppd(hw);
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else if (is_gen4_ntb(hw))
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/* PPD is in MMIO but not config space for NTB Gen4 */
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ret = intel_ntb4_check_ppd(hw);
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else {
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NTB_LOG(ERR, "Cannot init device for unsupported device.");
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return -ENOTSUP;
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}
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if (ret)
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return ret;
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hw->mw_cnt = XEON_MW_COUNT;
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hw->db_cnt = XEON_DB_COUNT;
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hw->spad_cnt = XEON_SPAD_COUNT;
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@ -149,15 +218,29 @@ intel_ntb_mw_set_trans(const struct rte_rawdev *dev, int mw_idx,
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rte_write64(base, xlat_addr);
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rte_write64(limit, limit_addr);
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/* Setup the external point so that remote can access. */
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xlat_off = XEON_EMBAR1_OFFSET + 8 * mw_idx;
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xlat_addr = hw->hw_addr + xlat_off;
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limit_off = XEON_EMBAR1XLMT_OFFSET + mw_idx * XEON_BAR_INTERVAL_OFFSET;
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limit_addr = hw->hw_addr + limit_off;
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base = rte_read64(xlat_addr);
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base &= ~0xf;
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limit = base + size;
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rte_write64(limit, limit_addr);
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if (is_gen3_ntb(hw)) {
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/* Setup the external point so that remote can access. */
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xlat_off = XEON_EMBAR1_OFFSET + 8 * mw_idx;
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xlat_addr = hw->hw_addr + xlat_off;
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limit_off = XEON_EMBAR1XLMT_OFFSET +
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mw_idx * XEON_BAR_INTERVAL_OFFSET;
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limit_addr = hw->hw_addr + limit_off;
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base = rte_read64(xlat_addr);
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base &= ~0xf;
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limit = base + size;
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rte_write64(limit, limit_addr);
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} else if (is_gen4_ntb(hw)) {
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/* Set translate base address index register */
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xlat_off = XEON_GEN4_IM1XBASEIDX_OFFSET +
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mw_idx * XEON_GEN4_XBASEIDX_INTERVAL;
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xlat_addr = hw->hw_addr + xlat_off;
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rte_write16(rte_log2_u64(size), xlat_addr);
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} else {
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NTB_LOG(ERR, "Cannot set translation of memory windows for unsupported device.");
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rte_write64(base, limit_addr);
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rte_write64(0, xlat_addr);
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return -ENOTSUP;
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}
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return 0;
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}
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@ -187,7 +270,7 @@ static int
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intel_ntb_get_link_status(const struct rte_rawdev *dev)
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{
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struct ntb_hw *hw = dev->dev_private;
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uint16_t reg_val;
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uint16_t reg_val, reg_off;
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int ret;
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if (hw == NULL) {
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@ -195,11 +278,20 @@ intel_ntb_get_link_status(const struct rte_rawdev *dev)
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return -EINVAL;
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}
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ret = rte_pci_read_config(hw->pci_dev, ®_val,
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sizeof(reg_val), XEON_LINK_STATUS_OFFSET);
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if (ret < 0) {
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NTB_LOG(ERR, "Unable to get link status.");
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return -EIO;
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if (is_gen3_ntb(hw)) {
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reg_off = XEON_GEN3_LINK_STATUS_OFFSET;
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ret = rte_pci_read_config(hw->pci_dev, ®_val,
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sizeof(reg_val), reg_off);
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if (ret < 0) {
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NTB_LOG(ERR, "Unable to get link status.");
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return -EIO;
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}
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} else if (is_gen4_ntb(hw)) {
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reg_off = XEON_GEN4_LINK_STATUS_OFFSET;
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reg_val = rte_read16(hw->hw_addr + reg_off);
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} else {
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NTB_LOG(ERR, "Cannot get link status for unsupported device.");
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return -ENOTSUP;
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}
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hw->link_status = NTB_LNK_STA_ACTIVE(reg_val);
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@ -216,9 +308,8 @@ intel_ntb_get_link_status(const struct rte_rawdev *dev)
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}
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static int
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intel_ntb_set_link(const struct rte_rawdev *dev, bool up)
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intel_ntb_gen3_set_link(const struct ntb_hw *hw, bool up)
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{
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struct ntb_hw *hw = dev->dev_private;
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uint32_t ntb_ctrl, reg_off;
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void *reg_addr;
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@ -241,6 +332,70 @@ intel_ntb_set_link(const struct rte_rawdev *dev, bool up)
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return 0;
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}
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static int
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intel_ntb_gen4_set_link(const struct ntb_hw *hw, bool up)
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{
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uint32_t ntb_ctrl, ppd0;
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uint16_t link_ctrl;
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void *reg_addr;
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if (up) {
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reg_addr = hw->hw_addr + XEON_NTBCNTL_OFFSET;
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ntb_ctrl = NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP;
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ntb_ctrl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP;
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rte_write32(ntb_ctrl, reg_addr);
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reg_addr = hw->hw_addr + XEON_GEN4_LINK_CTRL_OFFSET;
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link_ctrl = rte_read16(reg_addr);
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link_ctrl &= ~XEON_GEN4_LINK_CTRL_LINK_DIS;
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rte_write16(link_ctrl, reg_addr);
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/* start link training */
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reg_addr = hw->hw_addr + XEON_GEN4_PPD0_OFFSET;
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ppd0 = rte_read32(reg_addr);
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ppd0 |= XEON_GEN4_PPD_LINKTRN;
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rte_write32(ppd0, reg_addr);
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/* make sure link training has started */
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ppd0 = rte_read32(reg_addr);
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if (!(ppd0 & XEON_GEN4_PPD_LINKTRN)) {
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NTB_LOG(ERR, "Link is not training.");
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return -EINVAL;
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}
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} else {
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reg_addr = hw->hw_addr + XEON_NTBCNTL_OFFSET;
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ntb_ctrl = rte_read32(reg_addr);
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ntb_ctrl &= ~(NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP);
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ntb_ctrl &= ~(NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP);
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rte_write32(ntb_ctrl, reg_addr);
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reg_addr = hw->hw_addr + XEON_GEN4_LINK_CTRL_OFFSET;
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link_ctrl = rte_read16(reg_addr);
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link_ctrl |= XEON_GEN4_LINK_CTRL_LINK_DIS;
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rte_write16(link_ctrl, reg_addr);
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}
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return 0;
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}
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static int
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intel_ntb_set_link(const struct rte_rawdev *dev, bool up)
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{
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struct ntb_hw *hw = dev->dev_private;
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int ret = 0;
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if (is_gen3_ntb(hw))
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ret = intel_ntb_gen3_set_link(hw, up);
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else if (is_gen4_ntb(hw))
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ret = intel_ntb_gen4_set_link(hw, up);
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else {
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NTB_LOG(ERR, "Cannot set link for unsupported device.");
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ret = -ENOTSUP;
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}
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return ret;
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}
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static uint32_t
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intel_ntb_spad_read(const struct rte_rawdev *dev, int spad, bool peer)
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{
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@ -254,7 +409,16 @@ intel_ntb_spad_read(const struct rte_rawdev *dev, int spad, bool peer)
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}
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/* When peer is true, read peer spad reg */
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reg_off = peer ? XEON_B2B_SPAD_OFFSET : XEON_IM_SPAD_OFFSET;
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if (is_gen3_ntb(hw))
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reg_off = peer ? XEON_GEN3_B2B_SPAD_OFFSET :
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XEON_IM_SPAD_OFFSET;
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else if (is_gen4_ntb(hw))
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reg_off = peer ? XEON_GEN4_B2B_SPAD_OFFSET :
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XEON_IM_SPAD_OFFSET;
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else {
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NTB_LOG(ERR, "Cannot read spad for unsupported device.");
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return -ENOTSUP;
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}
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reg_addr = hw->hw_addr + reg_off + (spad << 2);
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spad_v = rte_read32(reg_addr);
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@ -275,7 +439,16 @@ intel_ntb_spad_write(const struct rte_rawdev *dev, int spad,
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}
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/* When peer is true, write peer spad reg */
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reg_off = peer ? XEON_B2B_SPAD_OFFSET : XEON_IM_SPAD_OFFSET;
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if (is_gen3_ntb(hw))
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reg_off = peer ? XEON_GEN3_B2B_SPAD_OFFSET :
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XEON_IM_SPAD_OFFSET;
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else if (is_gen4_ntb(hw))
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reg_off = peer ? XEON_GEN4_B2B_SPAD_OFFSET :
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XEON_IM_SPAD_OFFSET;
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else {
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NTB_LOG(ERR, "Cannot write spad for unsupported device.");
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return -ENOTSUP;
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}
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reg_addr = hw->hw_addr + reg_off + (spad << 2);
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rte_write32(spad_v, reg_addr);
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@ -308,6 +481,9 @@ intel_ntb_db_clear(const struct rte_rawdev *dev, uint64_t db_bits)
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db_off = XEON_IM_INT_STATUS_OFFSET;
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db_addr = hw->hw_addr + db_off;
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if (is_gen4_ntb(hw))
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rte_write16(XEON_GEN4_SLOTSTS_DLLSCS,
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hw->hw_addr + XEON_GEN4_SLOTSTS);
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rte_write64(db_bits, db_addr);
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return 0;
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@ -365,7 +541,14 @@ intel_ntb_vector_bind(const struct rte_rawdev *dev, uint8_t intr, uint8_t msix)
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}
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/* Bind intr source to msix vector */
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reg_off = XEON_INTVEC_OFFSET;
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if (is_gen3_ntb(hw))
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reg_off = XEON_GEN3_INTVEC_OFFSET;
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else if (is_gen4_ntb(hw))
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reg_off = XEON_GEN4_INTVEC_OFFSET;
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else {
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NTB_LOG(ERR, "Cannot bind vectors for unsupported device.");
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return -ENOTSUP;
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}
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reg_addr = hw->hw_addr + reg_off + intr;
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rte_write8(msix, reg_addr);
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@ -22,7 +22,7 @@
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#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
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#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
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/* Intel Skylake Xeon hardware */
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/* Intel Xeon hardware */
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#define XEON_IMBAR1SZ_OFFSET 0x00d0
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#define XEON_IMBAR2SZ_OFFSET 0x00d1
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#define XEON_EMBAR1SZ_OFFSET 0x00d2
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@ -31,7 +31,13 @@
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#define XEON_DEVSTS_OFFSET 0x009a
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#define XEON_UNCERRSTS_OFFSET 0x014c
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#define XEON_CORERRSTS_OFFSET 0x0158
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||||
#define XEON_LINK_STATUS_OFFSET 0x01a2
|
||||
#define XEON_GEN3_LINK_STATUS_OFFSET 0x01a2
|
||||
/* Link status and PPD are in MMIO but not config space for Gen4 NTB */
|
||||
#define XEON_GEN4_PPD0_OFFSET 0xb0d4
|
||||
#define XEON_GEN4_PPD1_OFFSET 0xb4c0
|
||||
#define XEON_GEN4_LINK_CTRL_OFFSET 0xb050
|
||||
#define XEON_GEN4_LINK_STATUS_OFFSET 0xb052
|
||||
#define XEON_GEN4_LINK_CTRL_LINK_DIS 0x0010
|
||||
|
||||
#define XEON_NTBCNTL_OFFSET 0x0000
|
||||
#define XEON_BAR_INTERVAL_OFFSET 0x0010
|
||||
@ -39,13 +45,18 @@
|
||||
#define XEON_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
|
||||
#define XEON_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
|
||||
#define XEON_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
|
||||
#define XEON_GEN4_XBASEIDX_INTERVAL 0x0002
|
||||
#define XEON_GEN4_IM1XBASEIDX_OFFSET 0x0074
|
||||
#define XEON_GEN4_IM2XBASEIDX_OFFSET 0x0076
|
||||
#define XEON_IM_INT_STATUS_OFFSET 0x0040
|
||||
#define XEON_IM_INT_DISABLE_OFFSET 0x0048
|
||||
#define XEON_IM_SPAD_OFFSET 0x0080 /* SPAD */
|
||||
#define XEON_GEN3_B2B_SPAD_OFFSET 0x0180 /* GEN3 B2B SPAD */
|
||||
#define XEON_GEN4_B2B_SPAD_OFFSET 0x8080 /* GEN4 B2B SPAD */
|
||||
#define XEON_USMEMMISS_OFFSET 0x0070
|
||||
#define XEON_INTVEC_OFFSET 0x00d0
|
||||
#define XEON_GEN3_INTVEC_OFFSET 0x00d0
|
||||
#define XEON_GEN4_INTVEC_OFFSET 0x0050
|
||||
#define XEON_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
|
||||
#define XEON_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
|
||||
#define XEON_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
|
||||
#define XEON_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
|
||||
#define XEON_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
|
||||
@ -70,6 +81,14 @@
|
||||
#define XEON_PPD_DEV_DSD 0x10
|
||||
#define XEON_PPD_SPLIT_BAR_MASK 0x40
|
||||
|
||||
#define XEON_GEN4_PPD_CONN_MASK 0x0300
|
||||
#define XEON_GEN4_PPD_CONN_B2B 0x0200
|
||||
#define XEON_GEN4_PPD_DEV_MASK 0x1000
|
||||
#define XEON_GEN4_PPD_DEV_DSD 0x1000
|
||||
#define XEON_GEN4_PPD_DEV_USD 0x0000
|
||||
#define XEON_GEN4_PPD_LINKTRN 0x0008
|
||||
#define XEON_GEN4_SLOTSTS 0xb05a
|
||||
#define XEON_GEN4_SLOTSTS_DLLSCS 0x100
|
||||
|
||||
#define XEON_MW_COUNT 2
|
||||
|
||||
|
||||
@ -50,6 +50,8 @@ intel_ioat_icx = {'Class': '08', 'Vendor': '8086', 'Device': '0b00',
|
||||
'SVendor': None, 'SDevice': None}
|
||||
intel_ntb_skx = {'Class': '06', 'Vendor': '8086', 'Device': '201c',
|
||||
'SVendor': None, 'SDevice': None}
|
||||
intel_ntb_icx = {'Class': '06', 'Vendor': '8086', 'Device': '347e',
|
||||
'SVendor': None, 'SDevice': None}
|
||||
|
||||
network_devices = [network_class, cavium_pkx, avp_vnic, ifpga_class]
|
||||
baseband_devices = [acceleration_class]
|
||||
@ -57,7 +59,7 @@ crypto_devices = [encryption_class, intel_processor_class]
|
||||
eventdev_devices = [cavium_sso, cavium_tim, octeontx2_sso]
|
||||
mempool_devices = [cavium_fpa, octeontx2_npa]
|
||||
compress_devices = [cavium_zip]
|
||||
misc_devices = [intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_ntb_skx, octeontx2_dma]
|
||||
misc_devices = [intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_ntb_skx, intel_ntb_icx, octeontx2_dma]
|
||||
|
||||
# global dict ethernet devices present. Dictionary indexed by PCI address.
|
||||
# Each device within this is itself a dictionary of device properties
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user