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crypto/qat: fix handle device-agnostic session

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Older generations of QuickAssist hardware
may not support all algorithms supported by newer
generations. When sessions were specific to the device
this only needed to be handled on session creation.
With device-agnostic sessions, a session created
for a newer device may get routed to an older device which
can't support it.
This patch adds an enum to define QAT device generations
and uses this to detect and handle the above case on the
data path.
It also renames the capabilities structures and #defines
to match the generation names and adds the generation
to the device table in the documentation.

Fixes: b3bbd9e5f2 ("cryptodev: support device independent sessions")

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This commit is contained in:
Arek Kusztal 2017-07-17 17:57:15 +01:00 committed by Pablo de Lara
parent 0b4b1e1b88
commit f51606537a
8 changed files with 53 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
doc/guides/cryptodevs/qat.rst
View File

@ -113,21 +113,21 @@ available kernel drivers and device ids are :
.. _table_qat_pmds_drivers:
.. table:: QAT devices and drivers
.. table:: QAT device generations, devices and drivers
+----------+--------+---------------+------------+--------+---------+--------+------------+
| Device | Driver | Kernel Module | Pci Driver | PF Did | Num PFs | Vf Did | VFs per PF |
+==========+========+===============+============+========+=========+========+============+
| DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |
+----------+--------+---------------+------------+--------+---------+--------+------------+
| DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
+----------+--------+---------------+------------+--------+---------+--------+------------+
| C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
+----------+--------+---------------+------------+--------+---------+--------+------------+
| C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
+----------+--------+---------------+------------+--------+---------+--------+------------+
| D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
+----------+--------+---------------+------------+--------+---------+--------+------------+
+-----+----------+--------+---------------+------------+--------+------+--------+--------+
| Gen | Device | Driver | Kernel Module | Pci Driver | PF Did | #PFs | Vf Did | VFs/PF |
+=====+==========+========+===============+============+========+======+========+========+
| 1 | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |
+-----+----------+--------+---------------+------------+--------+------+--------+--------+
| 1 | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
+-----+----------+--------+---------------+------------+--------+------+--------+--------+
| 2 | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
+-----+----------+--------+---------------+------------+--------+------+--------+--------+
| 2 | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
+-----+----------+--------+---------------+------------+--------+------+--------+--------+
| 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
+-----+----------+--------+---------------+------------+--------+------+--------+--------+
The ``Driver`` column indicates either the Linux kernel version in which

2
drivers/crypto/qat/qat_adf/qat_algs.h
View File

@ -51,6 +51,7 @@
#include "icp_qat_hw.h"
#include "icp_qat_fw.h"
#include "icp_qat_fw_la.h"
#include "../qat_crypto.h"
/*
* Key Modifier (KM) value used in KASUMI algorithm in F9 mode to XOR
@ -137,6 +138,7 @@ struct qat_session {
} auth_iv;
uint16_t digest_length;
rte_spinlock_t lock; /* protects this struct */
enum qat_device_gen min_qat_dev_gen;
};
int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);

2
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
View File

@ -606,6 +606,7 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
cipher_cd_ctrl->cipher_state_sz =
ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;
qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;
cdesc->min_qat_dev_gen = QAT_GEN2;
} else {
total_key_size = cipherkeylen;
cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
@ -858,6 +859,7 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
cdesc->cd_cur_ptr += state1_size + state2_size
+ ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;
auth_param->hash_state_sz = ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;
cdesc->min_qat_dev_gen = QAT_GEN2;
break;
case ICP_QAT_HW_AUTH_ALGO_MD5:

14
drivers/crypto/qat/qat_crypto.c
View File

@ -214,7 +214,7 @@ adf_modulo(uint32_t data, uint32_t shift);
static inline int
qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
struct qat_crypto_op_cookie *qat_op_cookie);
struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
void
qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
@ -492,6 +492,8 @@ qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
session->cd_paddr = rte_mempool_virt2phy(NULL, session) +
offsetof(struct qat_session, cd);
session->min_qat_dev_gen = QAT_GEN1;
/* Get requested QAT command id */
qat_cmd_id = qat_get_cmd_id(xform);
if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
@ -924,7 +926,7 @@ qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
while (nb_ops_sent != nb_ops_possible) {
ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
tmp_qp->op_cookies[tail / queue->msg_size]);
tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
if (ret != 0) {
tmp_qp->stats.enqueue_err_count++;
/*
@ -1081,7 +1083,7 @@ set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
static inline int
qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
struct qat_crypto_op_cookie *qat_op_cookie)
struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
{
int ret = 0;
struct qat_session *ctx;
@ -1117,6 +1119,12 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
return -EINVAL;
}
if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
return -EINVAL;
}
qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;

8
drivers/crypto/qat/qat_crypto.h
View File

@ -50,6 +50,11 @@
(((num) + (align) - 1) & ~((align) - 1))
#define QAT_64_BTYE_ALIGN_MASK (~0x3f)
enum qat_device_gen {
QAT_GEN1 = 1,
QAT_GEN2,
};
/**
* Structure associated with each queue.
*/
@ -77,6 +82,7 @@ struct qat_qp {
struct rte_mempool *op_cookie_pool;
void **op_cookies;
uint32_t nb_descriptors;
enum qat_device_gen qat_dev_gen;
} __rte_cache_aligned;
/** private data structure for each QAT device */
@ -85,6 +91,8 @@ struct qat_pmd_private {
/**< Max number of queue pairs supported by device */
unsigned max_nb_sessions;
/**< Max number of sessions supported by device */
enum qat_device_gen qat_dev_gen;
/**< QAT device generation */
const struct rte_cryptodev_capabilities *qat_dev_capabilities;
};

4
drivers/crypto/qat/qat_crypto_capabilities.h
View File

@ -34,7 +34,7 @@
#ifndef _QAT_CRYPTO_CAPABILITIES_H_
#define _QAT_CRYPTO_CAPABILITIES_H_
#define QAT_BASE_CPM16_SYM_CAPABILITIES \
#define QAT_BASE_GEN1_SYM_CAPABILITIES \
{ /* SHA1 HMAC */ \
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
{.sym = { \
@ -506,7 +506,7 @@
}, } \
}
#define QAT_EXTRA_CPM17_SYM_CAPABILITIES \
#define QAT_EXTRA_GEN2_SYM_CAPABILITIES \
{ /* ZUC (EEA3) */ \
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
{.sym = { \

5
drivers/crypto/qat/qat_qp.c
View File

@ -243,6 +243,11 @@ int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,
offsetof(struct qat_crypto_op_cookie,
qat_sgl_list_dst);
}
struct qat_pmd_private *internals
= dev->data->dev_private;
qp->qat_dev_gen = internals->qat_dev_gen;
dev->data->queue_pairs[queue_pair_id] = qp;
return 0;

16
drivers/crypto/qat/rte_qat_cryptodev.c
View File

@ -42,14 +42,14 @@
uint8_t cryptodev_qat_driver_id;
static const struct rte_cryptodev_capabilities qat_cpm16_capabilities[] = {
QAT_BASE_CPM16_SYM_CAPABILITIES,
static const struct rte_cryptodev_capabilities qat_gen1_capabilities[] = {
QAT_BASE_GEN1_SYM_CAPABILITIES,
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
static const struct rte_cryptodev_capabilities qat_cpm17_capabilities[] = {
QAT_BASE_CPM16_SYM_CAPABILITIES,
QAT_EXTRA_CPM17_SYM_CAPABILITIES,
static const struct rte_cryptodev_capabilities qat_gen2_capabilities[] = {
QAT_BASE_GEN1_SYM_CAPABILITIES,
QAT_EXTRA_GEN2_SYM_CAPABILITIES,
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
@ -122,12 +122,14 @@ crypto_qat_dev_init(struct rte_cryptodev *cryptodev)
internals->max_nb_sessions = RTE_QAT_PMD_MAX_NB_SESSIONS;
switch (RTE_DEV_TO_PCI(cryptodev->device)->id.device_id) {
case 0x0443:
internals->qat_dev_capabilities = qat_cpm16_capabilities;
internals->qat_dev_gen = QAT_GEN1;
internals->qat_dev_capabilities = qat_gen1_capabilities;
break;
case 0x37c9:
case 0x19e3:
case 0x6f55:
internals->qat_dev_capabilities = qat_cpm17_capabilities;
internals->qat_dev_gen = QAT_GEN2;
internals->qat_dev_capabilities = qat_gen2_capabilities;
break;
default:
PMD_DRV_LOG(ERR,